Floating-Gate Memory Layout Using Recessed Erase Gates
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Solution Overview
Problem
The increasing demand for high-capacity and low-cost semiconductor memory devices with complex fabrication processes necessitates the enhancement of memory cell integrity and density, which existing SONOS memory structures struggle to achieve due to limitations in miniaturization and design complexity.
Innovation Solution
The introduction of an erase gate partly disposed in a recess within an isolation structure reduces the dimension and area occupied by the memory device, allowing for more efficient memory cell design and integration by forming recesses in the isolation structures and positioning the erase gate accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the erase gate is disposed completely outside the isolation structure, then the fabrication process is simpler, but the memory cell dimension and occupied area are larger
Solution Approach 1:
The erase gate is partially nested within the isolation structure by forming a recess in the isolation structure and disposing the erase gate within this recess. This nesting approach allows the erase gate to be integrated into the existing isolation structure without requiring separate fabrication processes, thereby reducing the memory cell area while maintaining fabrication simplicity.
2Productivity
If the active regions are extended to reduce memory cell dimension, then the density is improved, but the fabrication process becomes more complex
Solution Approach 1:
Instead of extending active regions in the horizontal plane, the invention utilizes the vertical dimension by forming a recess in the isolation structure and positioning the erase gate within this recess. This dimensional approach reduces memory cell footprint and increases density without requiring complex horizontal extension processes.
3Ease of operation
If the erase gate is partly disposed in the recess within the isolation structure, then the memory cell dimension is reduced, but the fabrication precision requirement increases
Solution Approach 1:
The recess is formed in the isolation structure before the erase gate is disposed within it. This preliminary action establishes a pre-defined positioning structure that guides the erase gate placement, thereby reducing the actual positioning precision required during the erase gate formation process and simplifying the overall fabrication requirements.
Data Source
AI summary
A memory device includes a semiconductor substrate, isolation structures, an erase gate, and floating gates. The isolation structures are disposed in the semiconductor substrate. Active regions separated from one another are defined in the semiconductor substrate by the isolation structures, and each of the active regions is elongated in a first direction. The erase gate is disposed on the semiconductor substrate and elongated in a second direction. The erase gate is disposed on the active regions and the isolation structures, and the erase gate is partly disposed in a recess within each of the isolation structures. The floating gates are disposed on the semiconductor substrate. The floating gates are arranged in the second direction and separated from one another, and each of the floating gates is partly disposed under the erase gate in a vertical direction.