Planar Floating Gate Layout for Reliable Non-Volatile Erase
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Solution Overview
Problem
Conventional non-volatile memory devices face reliability issues during programming and erase operations due to damage to the tunneling oxide layer, which affects the efficiency and speed of data erasure.
Innovation Solution
A non-volatile memory device with a planar floating gate and an erase gate dielectric layer configuration, where the thickness of the coupling dielectric layer and the erase gate dielectric layer are optimized to create a favorable electric field for electron tunneling out of the planar floating gate during erase operations, enhancing the device's efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrons are injected into or pulled out of the floating gate through the tunneling oxide layer during programming or erase operations, then the operating speed and efficiency are increased, but the structure of the tunneling oxide layer is damaged and reliability is reduced
Solution Approach 1:
The patent introduces an erase gate as a separate component distinct from the control gate and floating gate. This segmentation allows independent control of electron injection and extraction operations, enabling electrons to be pulled out through a different path (tunneling oxide layer on the floating gate) than the path used for injection, thereby resolving the contradiction between speed/efficiency and reliability
Solution Approach 2:
The erase gate acts as an intermediary component that facilitates electron extraction from the floating gate. By introducing this intermediate element, the patent creates a dedicated electron extraction path that does not damage the tunneling oxide layer, while still maintaining high-speed operation capability
2Reliability
If an erase gate is added to pull electrons from the floating gate through the tunneling oxide layer on the floating gate, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the erase gate with the existing control gate structure, allowing the erase gate to share the same physical space and functional framework as the control gate. This merging approach minimizes additional structural complexity while still providing the reliability benefits of a dedicated electron extraction path
Solution Approach 2:
The control gate structure is designed to serve dual functions: as the control gate during normal programming operations and as the erase gate during erase operations. This multi-functionality reduces the need for completely separate structures, thereby limiting the increase in device complexity while improving reliability
3Productivity
If the coupling dielectric layer and erase gate dielectric layer thicknesses are optimized to create a favored electric field, then data erasure efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies concrete thickness parameter ranges for the coupling dielectric layer (50-200 nm) and erase gate dielectric layer (20-100 nm). By defining these specific parameter ranges, the patent optimizes electric field formation for high-speed erase operations while establishing clear manufacturing specifications that balance precision requirements with manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized dielectric layer thickness ratio improves the efficiency of data erasure by reducing stress on the tunneling oxide layer, thereby increasing the reliability and performance of the memory device.
Implementation Method 1
In order to create a favored electric field for making electrons tunnel out of the planar floating gate during an erase operation
Data Source
AI summary
A non-volatile memory device includes a memory cell including a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes a lateral tip laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric layer covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate, and includes a second thickness (T2). The erase gate covers the erase gate dielectric layer and the lateral tip of the planar floating gate. The first thickness and the second thickness satisfy the following relation: (T2)<(T1)<2(T2).