Floating-Gate Memory Cell Layout to Prevent Erase-Gate Shorting
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Solution Overview
Problem
Existing flash memory cells, such as ESF3, suffer from shorting issues between the erase gate line and the source line due to the need for a source line contact on the strap cell, leading to suboptimal performance and larger cell sizes.
Innovation Solution
The semiconductor memory device incorporates two floating gates with scallop-shaped surfaces facing an erase gate, enhancing electron release speed and reducing cell size through increased local electric field, and is fabricated using a Bosch etching process to form symmetrical memory gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source line contact is provided on the strap cell between two adjacent control gate lines, then the memory cell can be programmed and erased, but shorting occurs between the erase gate line and the source line
Solution Approach 1:
The invention removes the source line contact from the strap cell position between control gate lines, extracting the problematic element that caused shorting. The source line is repositioned to contact the substrate at locations away from the control gate lines, eliminating the shorting issue while preserving programming and erasing functions.
Solution Approach 2:
The invention introduces an insulating layer as an intermediary between the source line and the control gate lines. This intermediate structure prevents direct electrical contact that would cause shorting, while still allowing the source line to fulfill its function of supplying carriers to the floating gate during programming operations.
2Reliability
If conventional memory cell structures are used, then the device can operate, but the memory cell size is large
Solution Approach 1:
The invention transitions from a planar layout to a three-dimensional stacked structure, where control gates are positioned at different vertical levels. This dimensional change allows the memory cell components to be arranged more compactly in the vertical direction, reducing the horizontal footprint and overall cell area while maintaining full operational functionality.
Solution Approach 2:
The invention employs a nested arrangement where the first and second control gates are positioned above the floating gate in a stacked configuration, with the source line extending underneath. This nesting of functional elements in vertical and horizontal layers maximizes space utilization and minimizes the overall memory cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves electron releasing speed and erasing ability while reducing memory cell size, resulting in enhanced operational performance and device efficacy.
Implementation Method 1
enhancing electron release speed and reducing cell size through increased local electric field
Implementation Method 2
fabricated using a Bosch etching process to form symmetrical memory gates
Data Source
AI summary
A semiconductor memory device and a fabricating method thereof includes a substrate, two floating gates, two controlling gates, a first dielectric layer, two controlling gates, a spacer, and an erase gate. The floating gates are disposed on the substrate. The controlling gates are respectively disposed on the two floating gates. The first dielectric layer is disposed between the two floating gates and the two controlling gates in a vertical direction. The spacer is disposed on a sidewall of each of the two controlling gates. The erase gate is disposed on the substrate, between the two floating gates, wherein each of the two floating gates includes a sidewall with a scallop-shaped surface facing the erase gate.