Floating-Gate Memory Structure to Prevent Gate Silicide Shorting
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Solution Overview
Problem
The existing non-volatile semiconductor memory devices face issues with leakage current and short circuits due to overgrowth of silicide layers between the control gate and select gate, requiring excessive over-etching that decreases the select gate's cross-sectional area and increases its sharpness.
Innovation Solution
The solution involves forming a select gate with a height higher than the gate stack and a control gate silicide layer with a lateral length smaller than the control gate, along with spacers to prevent short circuits and maintain a distance between the silicide layers without excessive over-etching, thereby reducing the sharpness of the select gate shape.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excessive over-etching process is applied on the select gates to ensure space between control gate and select gate, then leakage current and short circuit are prevented, but the cross-sectional area of the select gates decreases and the sharpness of the select gates shape increases
Solution Approach 1:
A select gate insulating layer is formed on the sidewall of the gate stack before forming the select gate. This preliminary insulation layer prevents direct contact between the control gate and select gate silicide layers, allowing the select gate to maintain its cross-sectional area without excessive over-etching while still preventing leakage current and short circuits.
Solution Approach 2:
The select gate insulating layer acts as an intermediary barrier between the control gate and select gate silicide layers. This intermediate layer physically separates the two conductive elements, preventing harmful electrical interaction while allowing the select gate to retain its original shape and cross-sectional area.
2Reliability
If silicide layers are formed on the control gate and select gate to reduce resistance, then electrical conductivity is improved, but overgrowth of silicide layers between the control gate and select gate causes leakage current or short circuit
Solution Approach 1:
The gate structure is segmented into distinct regions with different properties. The select gate insulating layer creates a clear separation between the control gate region and the select gate silicide layer region. This segmentation allows silicide layers to be formed on both gates for conductivity while preventing their overgrowth from merging and causing short circuits.
Solution Approach 2:
The select gate insulating layer serves as an intermediary barrier that prevents the silicide layers from directly contacting each other. This intermediate insulation layer allows both the control gate and select gate to have low-resistance silicide contacts while preventing harmful electrical leakage between them.
Data Source
AI summary
A semiconductor device includes a source region and a drain region disposed in a substrate, a gate stack including a floating gate and a control gate disposed between the source region and the drain region, a select gate insulating layer disposed on a sidewall of the gate stack, and a select gate disposed on the select gate insulating layer, the select gate having a height higher than a height of the gate stack or a height of the control gate.