Floating-Gate Memory Cell for Single-Bit Addressing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory devices require lateral spatial doping to maximize channel conductivity, which is technically challenging and limits single bit addressing in arrays.
Innovation Solution
A memory cell design featuring a semiconductor substrate with a channel, control gate, and floating gate, where the floating gate is electrically isolated by charge barriers, enabling selective charge carrier passage through resonant tunnelling, eliminating the need for lateral spatial doping and allowing single bit addressing without applying a gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lateral spatial doping is used to maximize channel conductivity, then channel conductivity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and removes the lateral spatial doping step from the device fabrication process. Instead of doping the channel laterally to enhance conductivity, the invention uses a floating gate structure that provides the necessary electrical characteristics through charge storage, thereby eliminating the complex lateral doping process while maintaining reliable channel conduction.
Solution Approach 2:
The floating gate acts as an intermediary between the control gate and the channel. By introducing this intermediate structure that can store charge, the patent achieves the desired channel conductivity enhancement without requiring complex lateral spatial doping. The floating gate mediates the electrical interaction, providing a simpler alternative to direct channel modification.
2Reliability
If lateral spatial doping is applied to enhance channel conductivity, then conductivity is improved, but single bit addressing capability is lost
Solution Approach 1:
The patent removes lateral spatial doping from the device structure, which preserves the ability to perform single bit addressing. By eliminating this doping approach, each memory cell can be independently controlled and addressed without affecting adjacent cells, thereby maintaining ease of operation for single bit access while still achieving high channel conductivity through the floating gate mechanism.
Solution Approach 2:
The floating gate serves as an intermediary that enables independent control of each memory cell's channel conductivity. This intermediate charge storage structure allows precise single bit addressing by controlling charge injection into or removal from the floating gate, thereby enhancing channel conductivity on demand without the cross-talk issues that would arise from lateral spatial doping.
3Duration of action of stationary object
If conventional flash memory structure is used, then data retention is achieved, but write and erase speeds are limited
Solution Approach 1:
The patent applies parameter changes by modifying the electrical characteristics of the floating gate and its interaction with the channel. By optimizing the floating gate's charge storage capacity, the thickness and material properties of surrounding dielectric layers, and the voltage waveforms applied during write and erase operations, the invention achieves both fast switching speeds and long data retention. These parameter optimizations enable rapid charge injection and removal while maintaining stable charge storage.
Solution Approach 2:
The patent introduces dynamic control of the floating gate charge state to enable fast write and erase operations. The system transitions between charged and discharged states of the floating gate through controlled charge injection and removal processes, allowing rapid switching between logic states. This dynamic charge manipulation, combined with optimized electrical fields during operations, achieves high-speed performance while the floating gate's physical structure maintains long-term charge retention for data storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves non-volatile memory with fast write and erase speeds, reduced voltage requirements, and increased switching cycles, while maintaining data retention for extended periods without the need for lateral spatial doping.
Implementation Method 1
enabling selective passage of charge carriers into and out of the floating gate by resonant tunnelling
Data Source
AI summary
A memory cell comprises a floating gate being disposed between a control gate and a channel, the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate to provide occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between a control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.