Floating-Gate Memory Word Line Layout for Single Lithography
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Solution Overview
Problem
The semiconductor industry faces pressure to reduce the number of lithography processes in manufacturing new generations of integrated circuits, particularly for non-volatile memory cells, to lower costs while maintaining performance and functionality.
Innovation Solution
The method involves forming a stacked structure with a floating gate, control gate, and insulating layers in a non-volatile memory, where a conductive material layer is planarized and patterned using a mask to form word lines and an erase gate line, reducing the need for multiple lithography processes and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography processes are used to form word lines and erase gate lines separately, then patterning precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the formation of word lines and erase gate lines into a single lithography process by using a common mask pattern that defines both line types simultaneously. This merging approach reduces the total number of lithography steps from multiple separate processes to one unified process, thereby reducing manufacturing complexity and cost while maintaining acceptable patterning precision through optimized mask design and etch selectivity
2Manufacturing precision
If multiple lithography processes are used to form word lines and erase gate lines separately, then pattern definition accuracy is improved, but productivity decreases
Solution Approach 1:
The patent merges the patterning of word lines and erase gate lines into a single lithography step using a shared mask, which directly increases manufacturing efficiency by reducing the total process time and number of steps. The pattern definition accuracy is maintained through careful mask design that accounts for the different functions and spacing requirements of word lines and erase gate lines, ensuring both line types are accurately defined in one pass
3Manufacturing precision
If separate lithography processes are used for word lines and erase gate lines, then process control is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the lithography processes for word lines and erase gate lines into a single step, which reduces manufacturing cost by eliminating redundant process equipment usage, material consumption, and labor. Process control is maintained through optimized etch selectivity ratios that allow both line types to be formed with appropriate precision from the same mask pattern, and through careful parameter optimization for the unified process
4Ease of manufacture
If a simplified single lithography process is used to form both word lines and erase gate lines, then manufacturing cost is reduced, but patterning precision may deteriorate
Solution Approach 1:
The patent merges the formation of word lines and erase gate lines into one lithography process to reduce manufacturing cost. To maintain patterning precision, the invention employs optimized mask design with appropriate pattern spacing, selective etch chemistry with high selectivity ratios, and controlled etch parameters that ensure both line types achieve the required dimensional accuracy and critical dimension uniformity despite being formed in a single process step
Data Source
AI summary
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.