Sub-lithographic Floating Gate Spacing for Flash Memory
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Solution Overview
Problem
The challenge in scaling flash memory cells is to achieve the desired coupling between control and floating gates while avoiding interference between adjacent floating gates, which is difficult due to the narrow spacing required.
Innovation Solution
The method involves forming semiconductor constructions with sub-lithographic width floating gates, where the floating gates are spaced farther apart than the active areas, using a process that includes forming isolation regions, gate dielectric, and spacer formation to create 'I'-shaped floating gates with a larger pitch than the active areas, reducing cross-coupling between adjacent flash memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If floating gates are spaced closer together to increase integration density, then the number of devices per area increases, but interference between adjacent floating gates increases
Solution Approach 1:
The patent introduces a vertical dimension by forming spacers that extend upward from the substrate surface, creating a three-dimensional structure. This allows the floating gates to be spaced farther apart horizontally while maintaining high integration density through vertical utilization of space. The spacers provide physical separation in the vertical dimension, effectively reducing interference between adjacent floating gates.
Solution Approach 2:
The patent introduces spacers as intermediary structures between adjacent floating gates. These spacers act as mediators that physically separate the floating gates and control the spacing between them. The spacers are formed from insulating material and extend vertically to provide adequate isolation, preventing interference while allowing compact horizontal spacing.
2Ease of manufacture
If floating gates are formed with standard lithographic width, then manufacturing is simpler, but cross-coupling between adjacent cells increases due to narrow spacing requirements
Solution Approach 1:
The patent segments the floating gate structure into multiple components: a base portion formed by lithography and additional portions formed by spacer-based self-aligned processes. This segmentation allows different portions of the floating gate to be formed with different precision requirements, reducing overall manufacturing difficulty while achieving the needed spacing control.
Solution Approach 2:
The patent performs preliminary actions by forming spacers and isolation regions before completing the floating gate structure. These preliminary structures establish the spacing framework that guides subsequent floating gate formation, ensuring proper separation is achieved before the actual gate material is deposited and patterned.
Data Source
AI summary
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.