Floating Gate Spacing for OTPROM Data Retention
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Solution Overview
Problem
Existing nonvolatile memory technologies face issues with data retention characteristics due to variations in manufacturing parameters, such as mask misalignment and process variations, leading to charge leakage and reduced reliability in OTPROMs.
Innovation Solution
The solution involves setting different design rules for the distance between the floating gate and signal lines in memory cell transistors compared to peripheral transistors, ensuring a sufficient electric field to prevent charge leakage, while maintaining the same manufacturing steps for both memory and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same design rule is applied to both memory cell transistors and peripheral transistors, then manufacturing complexity is reduced and ease of manufacture is improved, but data retention characteristics deteriorate due to charge leakage from insufficient electric field in memory cells
Solution Approach 1:
The patent applies different design rules to different regions of the semiconductor device. Specifically, a first design rule is applied to memory cell transistors that ensures a sufficient distance between the floating gate and signal lines to maintain an electric field strong enough to prevent charge leakage. A second, less restrictive design rule is applied to peripheral transistors. This local differentiation resolves the contradiction by optimizing each region for its specific function while maintaining overall manufacturability.
2Manufacturing precision
If mask alignment precision is improved to reduce misalignment, then manufacturing precision is improved, but manufacturing cost and complexity increase, and the benefit is limited since some misalignment always occurs
Solution Approach 1:
The patent incorporates a preliminary design consideration that anticipates potential mask misalignment. By pre-establishing a larger safety margin (greater distance) between the floating gate and signal lines in the memory cell region, the design proactively compensates for expected manufacturing variations. This preliminary action ensures that even when misalignment occurs, the electric field remains sufficient to prevent charge leakage, thereby resolving the contradiction without requiring excessive manufacturing precision.
3Reliability
If the distance between floating gate and signal lines is increased to prevent charge leakage, then data retention characteristics are improved, but device area increases and integration density decreases
Solution Approach 1:
The patent implements spatially differentiated design rules where only the memory cell transistor region employs the stricter spacing requirement to prevent charge leakage. The peripheral transistor region maintains standard spacing, allowing for higher density. This localized approach ensures data retention reliability where needed while minimizing overall device area impact, thus resolving the contradiction between reliability and area.
Data Source
AI summary
Distance λm between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance λ determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of a programmable memory which stores data in accordance with the amount of accumulated charges in the floating gate can be ensured without being affecting by mask misalignment or the like.