Floating Gate Transistor Surface Channel Regions Reduce Off-State Leakage
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Solution Overview
Problem
Buried channel devices in non-volatile memory cells exhibit high off-state current leakage, which reduces the operating margin and lifetime, and existing solutions to increase the on-to-off current ratio either increase programming voltage and time or expand memory cell area, making it challenging to achieve high bit density.
Innovation Solution
A non-volatile memory cell design incorporating a floating gate transistor with surface channel regions formed at the ends of the floating gate, interposed between a buried channel region, which increases the energy barrier and threshold voltage, reducing off-state current leakage without increasing physical channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a buried channel region is used in floating gate transistors to achieve lower noise and higher drive current, then the on current increases, but the off state current leakage increases significantly
Solution Approach 1:
The channel region is segmented into two distinct parts: a buried channel region for providing high drive current and low noise, and surface channel regions at the ends for providing high threshold voltage and low off-state leakage. This segmentation allows each region to optimize for its specific function without compromising the other.
Solution Approach 2:
Different regions of the channel are given different doping characteristics and depths. The buried channel region is implanted at a first depth with specific doping concentration for high mobility, while surface channel regions are formed at the ends with different doping characteristics to increase threshold voltage locally, reducing off-state leakage only where needed.
2Object-generated harmful factors
If the channel length is increased to reduce off state current leakage, then the leakage decreases, but the memory cell area increases
Solution Approach 1:
Instead of uniformly increasing channel length across the entire channel, the invention applies threshold voltage enhancement only at the critical end regions where leakage occurs. This localized approach reduces leakage effectively while maintaining a compact overall channel length and small memory cell area.
3Object-generated harmful factors
If the threshold voltage is increased to reduce off state current leakage, then the leakage decreases, but the programming voltage and programming time increase
Solution Approach 1:
The threshold voltage enhancement is segmented to affect only the end regions through surface channel formation, rather than increasing the threshold voltage uniformly across the entire channel. This localized enhancement reduces leakage without requiring a substantial increase in overall programming voltage or time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces off-state current leakage by up to six orders of magnitude, improving the operating margin and memory cell performance while maintaining or exceeding the performance of longer channel devices with reduced physical channel length, thus enhancing bit density and memory cell reliability.
Implementation Method 1
increases the energy barrier and threshold voltage, reducing off-state current leakage
Data Source
AI summary
In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.