Floating Gate Test Structure Cell-like Layout Height Mismatch
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Solution Overview
Problem
The existing method for manufacturing integrated circuits (ICs) with embedded memory technology faces challenges due to the height mismatch between the floating gate test device and memory cell structures, which leads to potential damage and electrical shorting during the formation of logic device structures, especially in future process nodes.
Innovation Solution
A method is introduced to form a floating gate test device with a cell-like top layout, comprising islands and bridges, to prevent etch-back material accumulation and ensure equal thickness of the etch-back layer, thereby maintaining the integrity of the floating gate test device and memory cell structures during the formation of logic device structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional floating gate test device structure is used, then the test device can be formed, but height mismatch occurs between the floating gate test device and memory cell structures, leading to potential damage and electrical shorting during logic device structure formation
Solution Approach 1:
The floating gate test device structure is segmented into multiple levels with different heights, matching the height of corresponding memory cell structures at each level. This segmentation allows the etch-back layer to have uniform thickness across different structure types, preventing material accumulation and electrical shorting while maintaining test device integrity during logic device structure formation
Solution Approach 2:
Different portions of the floating gate test device are given different local heights to match the local height requirements of underlying memory cell structures. The first floating gate test device portion is formed at a first height matching a first memory cell structure, while a second floating gate test device portion is formed at a second height matching a second memory cell structure, ensuring uniform etch-back layer thickness and preventing structural damage
2Ease of manufacture
If the floating gate test device structure height does not match memory cell structure height, then manufacturing is simpler, but etch-back material accumulates leading to damage and electrical shorting
Solution Approach 1:
The floating gate test device is divided into multiple portions with different heights that correspond to different memory cell structure heights. This segmentation ensures that the etch-back layer can be formed with uniform thickness across all structures, preventing material accumulation that would otherwise cause damage and electrical shorting during subsequent processing steps
3Manufacturing precision
If extra reticles or photomasks are used to solve height mismatch, then manufacturing precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The floating gate test device structure is designed to serve multiple functions: it provides test structures at different heights that match different memory cell structures, enables uniform etch-back layer formation, and eliminates the need for separate processing steps with extra reticles or photomasks. This multi-functional design achieves manufacturing precision without increasing process complexity
Data Source
AI summary
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.