Floating Gate Test Structure Concurrent Fabrication
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Solution Overview
Problem
The existing methods for manufacturing integrated circuits (ICs) with embedded memory technology require additional photolithography processes for forming floating gate test structures, which complicates the fabrication process and increases costs.
Innovation Solution
A method is developed to form the floating gate test structure concurrently with the memory cell structure by patterning a multilayer film on the memory region, using dummy components that are later removed, thereby eliminating the need for separate photolithography and etching processes for the floating gate test structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional photolithography processes are used to form floating gate test structures, then the floating gate test structure can be formed with high precision, but the fabrication process complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the formation of memory cell structures and floating gate test structures into a single photolithography process. By designing the photomask to include patterns for both memory cells and test structures, and using a unified fabrication sequence, the patent eliminates the need for separate photolithography steps, thereby reducing process complexity while maintaining formation precision
Solution Approach 2:
The patent creates a universal fabrication process that serves dual purposes: forming functional memory cell structures and test structures simultaneously. The same photolithography patterns, etching conditions, and deposition steps are used for both memory cells and test structures, making the process multi-functional and reducing overall complexity
2Manufacturing precision
If additional photolithography processes are used to form floating gate test structures, then the floating gate test structure can be formed with high precision, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple manufacturing operations into a single integrated process flow. By forming test structures and memory cells in the same photolithography and etching sequence, the patent reduces the total number of process steps, which directly lowers manufacturing costs while preserving the precision required for test structure formation
3Adaptability or versatility
If separate photolithography processes are used for floating gate test structure, then the test structure can be formed independently, but the fabrication process time increases
Solution Approach 1:
The patent merges the formation sequences of memory cells and test structures into a single continuous fabrication process. Both structures are patterned, etched, and filled simultaneously in the same process window, eliminating the time required for separate processing while maintaining the ability to independently design and form test structures
Data Source
AI summary
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device, as well as a method for forming the IC. In some embodiments, the IC comprises a memory cell structure including a pair of control gates respectively separated from a substrate by a pair of floating gates and a pair of select gate electrodes disposed on opposite sides of the pair of control gates. A memory test structure includes a pair of dummy control gates respectively separated from the substrate by a pair of dummy floating gates and a pair of dummy select gate electrodes disposed on opposite sides of the pair of dummy control gates. The memory test structure further includes a pair of conductive floating gate test contact vias respectively extending through the pair of dummy control gates and reaching on the dummy floating gates.