Floating Gate Transistor Threshold Control for Memory Cell Area Reduction
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently performing erasing and writing operations, particularly in reducing voltage and time requirements, while also minimizing memory cell area.
Innovation Solution
The semiconductor device incorporates a memory cell with a first source and drain region, a selection gate, and a floating gate, where the threshold of the floating gate transistor is lowered by applying zero or negative voltage to the drain region, and a second gate portion is used to extract electric charge and raise the threshold, enabling efficient erasing and writing operations. Additionally, the floating gate has a planner shape with a recessed portion to increase coupling capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the threshold of the floating gate transistor is lowered to enable efficient erasing operation, then the erasing operation can be performed with reduced voltage and time, but the memory cell area increases due to additional structure requirements
Solution Approach 1:
The patent merges the selection gate and floating gate into a shared gate structure where the selection gate can serve dual purposes: selecting memory cells during read operations and enabling erasure operations when appropriate voltages are applied. This integration eliminates the need for completely separate gate structures, thereby reducing memory cell area while maintaining efficient erasing capability.
Solution Approach 2:
The selection gate is designed to perform multiple functions: it acts as a selection gate during normal read operations, serves as a control gate for erasing operations by applying negative voltage, and participates in write operations. This multi-functionality allows the patent to achieve efficient erasing without adding dedicated erasure gate structures, thus avoiding area increase.
2Ease of manufacture
If a single poly NVM structure is used to reduce fabrication process steps, then manufacturing complexity is reduced, but the ability to perform efficient erasing operations with reduced voltage and time is limited
Solution Approach 1:
The patent modifies the electrical parameters of the single poly NVM structure by applying specific voltage sequences: negative voltage to the selection gate and positive voltage to the control gate during erasing operations. These parameter changes enable Fowler-Nordheim tunneling for efficient charge removal from the floating gate, achieving fast erasing without requiring additional fabrication steps or multiple polysilicon layers.
Solution Approach 2:
The patent replaces complex multi-layer gate structures with a simplified single polysilicon gate structure that achieves the same erasing function through electrical field control. By using voltage-controlled Fowler-Nordheim tunneling instead of physical structure complexity, the patent maintains manufacturing simplicity while achieving efficient erasing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances operation efficiency and reduces the area of the memory cell, allowing for efficient erasing and writing operations while stabilizing potential fluctuations.
Implementation Method 1
an electric charge storage floating gate having a polysilicon single layer is formed
Implementation Method 2
The threshold of the first floating gate transistor may be lowered by applying a zero voltage or a negative voltage to the first drain region and lowering a potential level of the first floating gate
Implementation Method 3
the threshold of the first floating gate transistor may be raised due to hot carriers by applying a positive voltage to the first drain region and applying a positive voltage to the second region
Data Source
AI summary
A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.