Floating Gate Tip Protection via Oxide Cap and Spacer Layer
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Solution Overview
Problem
The existing manufacturing processes for flash memory cells result in dulling or blunting of floating gate tips during the source dopant implant, which decreases the efficiency of erase and program operations due to inadequate protection of the tips from dopant penetration.
Innovation Solution
A flat-topped oxide cap and a nitride spacer layer are formed over the floating gate structure to protect the upwardly-pointing tips from dopant penetration during the source implant, allowing for self-aligned implantation and reducing tip dulling or blunting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a source dopant implant is performed without additional protection layers, then the implantation process can be completed, but the floating gate tips become dulled or blunted due to dopant penetration
Solution Approach 1:
A flat-topped oxide cap is formed over the floating gate structure before the source dopant implantation process. This oxide cap serves as a protective barrier that prevents dopant penetration into the floating gate tips during implantation, thereby maintaining tip sharpness and preventing dulling or blunting.
Solution Approach 2:
The oxide cap acts as an intermediary protective layer between the source dopant implantation process and the floating gate structure. It absorbs or blocks the harmful dopant particles, preventing them from reaching and damaging the floating gate tips while allowing the implantation process to proceed.
2Productivity
If higher source implant energy is used to ensure adequate dopant penetration, then implantation efficiency improves, but floating gate tip dulling increases
Solution Approach 1:
The oxide cap is formed in advance before implantation, providing a protective barrier that enables the use of higher implant energies without damaging the floating gate tips. This preliminary protection allows optimization of implantation efficiency while maintaining tip sharpness.
Solution Approach 2:
The oxide cap, which might be considered an additional process step or complexity, actually enables higher implant energies to be used beneficially. The cap absorbs the harmful high-energy dopant impact, converting what would be damaging energy into a controlled process parameter that improves implantation efficiency without side effects.
3Ease of manufacture
If no oxide cap is formed, then the manufacturing process is simpler, but dopant penetration causes tip dulling that reduces cell efficiency
Solution Approach 1:
The oxide cap is formed as a preliminary step before source implantation, providing essential protection that ensures reliable erase and program operations. This upfront action prevents tip dulling that would otherwise degrade cell performance, making the additional process step necessary for achieving the desired reliability.
Solution Approach 2:
The oxide cap serves as a cushioning layer formed beforehand to absorb or block dopant penetration during implantation. This prior protection prevents the harmful effects of dopant exposure, ensuring that the floating gate tips maintain their sharpness and the cell maintains high operational efficiency for erase and program operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents or reduces the dulling of floating gate tips, maintaining their acuteness and improving the operational efficiency of flash memory cells by allowing lower source implant energy and better control over diffusion lengths.
Implementation Method 1
A flat-topped oxide cap and a nitride spacer layer are formed over the floating gate structure to protect the upwardly-pointing tips from dopant penetration during the source implant
Implementation Method 2
the floating gate is formed by a Poly1 layer, while the program/erase gate is formed by a Poly2 layer that partially overlaps the underlying Poly1 floating gate in the lateral direction. For some memory cells, the manufacturing process includes a floating gate thermal oxidation process that forms a football-shaped oxide over the Poly1 floating gate
Implementation Method 3
followed by an anneal process that diffuses the source dopant outwardly such that the resulting source region extends partially under the floating gate 14
Data Source
AI summary
A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.