Floating-Gate Transistor Current-Mode Computation for Tensor Operations
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Solution Overview
Problem
Existing digital neural network devices face challenges in efficiently executing large-scale transistor tensor operations due to high computational costs, power consumption, and inflexibility, particularly in supporting multiple levels of matrix computations and configurations, which limits their performance and scalability.
Innovation Solution
The use of floating-gate transistors configured as current-mode computation cells and current-mode summation circuits allows for parallel execution of transistor tensor operations, including matrix-vector and tensor contractions, with field-programmable capabilities to support multiple levels and configurations, leveraging the programmable threshold voltage properties of floating-gate transistors for efficient weighted summations and activation functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If digital neural network devices use traditional digital computation circuits to execute large-scale transistor tensor operations, then computational accuracy is maintained, but computational cost and power consumption increase significantly
Solution Approach 1:
The patent replaces traditional digital computation circuits with floating-gate transistor-based current-mode computation cells. These cells leverage the physical properties of floating-gate transistors (threshold voltage control and current modulation) to directly perform tensor operations, substituting complex digital logic with simpler analog-like computation that consumes less power and executes faster
Solution Approach 2:
The patent changes the operational parameters of the computation cells by using floating-gate transistors with programmable threshold voltages. This allows the same hardware structure to perform different computational functions by adjusting voltage parameters rather than reconfiguring digital logic, reducing both power consumption and computational overhead
2Adaptability or versatility
If digital neural network devices use fixed-configuration computation circuits, then manufacturing simplicity is maintained, but adaptability to different neural network configurations is limited
Solution Approach 1:
The patent designs floating-gate transistor computation cells that can perform multiple neural network operations (matrix-vector multiplication, tensor contractions, activation functions) using the same basic circuit structure. The universal cell design achieves adaptability through parameter programming rather than structural reconfiguration, maintaining manufacturing simplicity while supporting diverse neural network configurations
Solution Approach 2:
The patent introduces dynamic configurability through programmable threshold voltages of floating-gate transistors. This allows the computation cells to be dynamically reconfigured for different neural network architectures and operations without changing the physical circuit structure, achieving versatility while keeping the device design relatively simple
3Speed
If traditional digital circuits are used for tensor operations, then ease of manufacture is maintained, but execution speed and performance are limited
Solution Approach 1:
The patent substitutes slow digital logic operations with faster floating-gate transistor current-mode operations. The computation cells execute tensor operations in parallel using current summation rather than sequential digital addition, achieving significantly higher execution speeds while remaining compatible with standard semiconductor manufacturing processes
Solution Approach 2:
The patent merges computation and memory functions into the same floating-gate transistor structure. The computation cells simultaneously store weights (in threshold voltage) and perform computation (through current modulation), eliminating the need for separate memory and computation units and simplifying the overall device architecture while improving performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces computational costs and power consumption while enhancing performance, enabling faster and more flexible execution of neural network computations, comparable to thousands of operations per second with reduced energy expenditure.
Implementation Method 1
leveraging the programmable threshold voltage properties of floating-gate transistors for efficient weighted summations and activation functions
Implementation Method 2
A branch summation line may produce a branch output current that is a current-mode summation of the received CMC cell output currents
Implementation Method 3
An individual layer-one current summation circuit may comprise a feedback circuit that can limit at least an amplitude of the received branch output current
Data Source
AI summary
An integrated circuit includes a plurality of current-mode computation (CMC) branches, each including a plurality of CMC cells and a branch summation line. An individual CMC cell includes at least one computation transistor that produces a CMC output current that is a function of a channel current of the computation transistor. A branch summation line receives CMC cell output currents produced by a plurality of CMC cells, and produces a branch output current that is a current-mode summation of all received CMC cell output currents. A layer-one current summation circuit receives the branch output current produced by at least one branch summation line, and produces a layer-one current summation circuit output current that is a function of the received branch output currents. The layer-one current summation circuit may be field-programmable. In operation, the integrated circuit can perform transistor tensor operations by programming one or more layer-one current summation circuits to combine all branch output currents received by those layer-one current summation circuits. Using embodiments of the present invention, millions, billions, trillions or more of the CMC cells can be field-programmed to execute computations in parallel to support transistor tensor operations.