Floating Gate Shallow Trench Isolation Height Difference Reduction
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Solution Overview
Problem
Conventional nonvolatile memory manufacturing methods face challenges in forming contact holes due to the height difference between memory and logic regions, leading to reduced process margins, especially when integrating flash memory with logic elements on a single chip.
Innovation Solution
A method involving selective etching of shallow trench isolation (STI) films to form a floating gate and a common source under the floating gate, reducing height differences and simplifying the manufacturing process by eliminating the need for photolithography in forming the floating gate, and using Fowler-Nordheim tunneling for data erasing and writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a floating gate is formed on the silicon substrate using conventional methods, then the memory structure is complete, but the height difference between memory region and logic region increases, reducing process margin for contact hole formation
Solution Approach 1:
The patent applies local quality by forming the floating gate within a shallow trench isolation structure rather than directly on the substrate. This localized approach creates a depression in the memory region that reduces the height difference between memory and logic regions, thereby improving contact margin while maintaining the necessary floating gate functionality
Solution Approach 2:
The patent transitions from a planar floating gate structure to a three-dimensional structure by embedding the floating gate within a trench. This dimensional change allows the floating gate to be positioned at a lower elevation, reducing the height differential between memory and logic regions and improving subsequent contact hole formation process margin
2Reliability
If memory cells are separated by a designated interval to prevent leakage current and short channel effects, then reliability improves, but cell size increases
Solution Approach 1:
The patent merges the isolation function with the floating gate structure by forming the floating gate within the shallow trench isolation region. This combination eliminates the need for separate isolation structures between cells, reducing cell area while maintaining the reliability benefits of isolation through the trench structure that prevents leakage current and short channel effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures assured contact and electrical margins, reduces cell area, and simplifies the manufacturing process by patterning the control gate with the logic gate, while preventing leakage current and short channel effects.
Implementation Method 1
etching the oxidation film in the second trench so that the oxidation film remains at the central portion of the second trench
Implementation Method 2
a tunnel oxidation film is formed in the second trench from which the oxidation film is etched
Implementation Method 3
the data erasing and writing operations of which are performed by Fowler-Nordheim tunneling
Data Source
AI summary
A method for manufacturing and operating a nonvolatile memory in which a floating gate is formed on a silicon substrate to reduce the difference in heights between a memory region and a logic region so that a process margin is assured. The method includes forming first trenches having a designated depth and a second trench having a depth smaller than that of the first trenches, and filling the first and second trenches with an oxidation film; planarizing the oxidation film, and etching the oxidation film in the second trench so that the oxidation film remains at the central portion of the second trench; forming a tunnel oxidation film in the second trench from which the oxidation film is etched, and depositing a first polysilicon film thereon; etching the first polysilicon film back so that a 2-bit floating gate is formed in the second trench; removing the oxidation film in the second trench by wet etching, and forming a common source on the silicon substrate under the second trench by depositing a lower oxidation film and using the lower oxidation film as a buffer film; depositing a nitride film and an upper oxidation film on the resulting structure provided with the deposited common source; depositing a second polysilicon film on the entire surface of the upper oxidation film; and forming a control gate by etching the second polysilicon film.