Floating Gate Uniformity via Dummy Hard Mask Slots
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Solution Overview
Problem
The integration of memory and logic circuits on a single substrate in semiconductor manufacturing often results in non-uniform floating gate structures due to chemical-mechanical polishing (CMP) processes, leading to performance degradation and reliability issues.
Innovation Solution
The use of a dummy pattern hard mask with slots in the boundary region during the CMP process to balance etching rates and achieve uniform thickness of floating gates across the memory array region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chemical-mechanical polishing (CMP) process is used for planarization, then manufacturing efficiency is improved, but floating gate uniformity deteriorates due to dishing effects
Solution Approach 1:
The patent applies local quality by creating a non-uniform hard mask thickness distribution across the substrate. The hard mask is thicker at the substrate center and thinner at the edges, which compensates for the differential etching rates during CMP. This local variation in hard mask properties balances the etching uniformity across different regions of the substrate, preventing dishing effects while maintaining manufacturing efficiency.
Solution Approach 2:
The patent implements preliminary action by pre-forming the hard mask layer with a specific non-uniform thickness profile before the CMP process. This preliminary structuring of the hard mask layer anticipates and compensates for the dishing effects that will occur during subsequent CMP, ensuring uniform floating gate formation without requiring process modification.
2Manufacturing precision
If hard mask thickness is increased at substrate center, then etching uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the thickness parameter of the hard mask layer across different spatial locations. Specifically, the hard mask thickness is varied from the substrate center to the edges, creating a gradient profile that optimizes etching uniformity. This continuous parameter variation simplifies the overall process by using a single hard mask layer with controlled thickness variation rather than multiple layers or complex patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures more uniform floating gate thickness from the center to the edge of the memory array region, enhancing the reliability and performance of integrated circuits by preventing 'dishing' effects during planarization.
Implementation Method 1
chemical-mechanical polishing (CMP) processes
Data Source
AI summary
The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.