Floating Guard Ring for High Voltage Interconnect Field Control
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Solution Overview
Problem
Conventional high voltage gate driver integrated circuits face challenges in designing power devices that integrate with low voltage devices effectively, leading to issues such as high electric fields, snapback, and breakdown degradation due to the connection of metal interconnects across high voltage regions, and increased manufacturing costs from additional processing steps for buried layers.
Innovation Solution
The integration of a guard structure in the semiconductor layer under the interconnect structure, which is electrically floating and acts between the driver circuit and the level shifter, helps in reducing the electric field and preventing snapback by wrapping the depletion around the guard structure, thereby improving breakdown voltage and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal interconnect is used to connect level shifter to high voltage circuit region, then electrical connection is achieved, but high electric field causes snapback and breakdown degradation
Solution Approach 1:
An N-type guard ring structure is introduced as an intermediary element between the metal interconnect and the high voltage circuit region. This guard ring acts as a mediator that intercepts and redistributes the electric field lines, preventing direct field concentration at the interconnect-high voltage region interface. The guard ring is doped to create a depletion region that wraps around the interconnect, effectively shielding the underlying silicon from high electric field stress.
Solution Approach 2:
The doping concentration and geometric parameters of the guard ring are optimized to control the depletion region extent. By adjusting the guard ring's doping level and dimensions, the depletion region is engineered to extend sufficiently to wrap around the metal interconnect, creating an electric field distribution that prevents snapback while maintaining proper electrical connection.
2Reliability
If level shifter is merged into high voltage circuit region, then breakdown degradation is avoided, but leakage current between LDMOS drain and high voltage region increases
Solution Approach 1:
The level shifter structure is segmented into distinct regions with different doping characteristics. The guard ring creates a spatial separation between the LDMOS drain region and the high voltage circuit region, forming an intermediate zone that prevents direct carrier injection while maintaining electrical connectivity through the controlled depletion region.
3Reliability
If N-type buried layer structure is formed in high voltage and low voltage regions, then parasitic PNP conduction is reduced and latch-up is prevented, but manufacturing complexity and cost increase
Solution Approach 1:
The N-type guard ring structure serves multiple functions simultaneously: it prevents snapback by controlling electric field distribution, reduces leakage current through proper depletion management, and prevents latch-up by maintaining appropriate doping profiles. This multi-functional approach eliminates the need for separate buried layer structures in high voltage regions, as the guard ring itself provides the necessary protection mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a guard structure effectively mitigates high electric field issues and breakdown degradation, enhancing the reliability and efficiency of high voltage integrated circuits while simplifying the manufacturing process by reducing the need for additional processing steps.
Implementation Method 1
wrapping the depletion around the guard structure
Implementation Method 2
reducing the electric field and preventing snapback
Data Source
AI summary
Aspects of the present disclosure describe an integrated circuit comprises a substrate of a first conductivity type semiconductor, a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate, a driver circuit, an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end, at least one guard structure formed in the semiconductor layer and under the interconnect structure and a well region of the first conductivity type semiconductor formed in a top portion of the semiconductor layer, between the driver circuit and the at least one guard structure and under the interconnect structure. The guard structure is electrically floating. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.