Floating Input Bias Circuit Without Static Current Draw
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Solution Overview
Problem
Existing circuits face challenges in detecting a floating state without static current consumption, particularly in low-power applications, as they require a pull-down impedance that consumes power even when the switch is closed.
Innovation Solution
A floating state detection circuit using MOS transistors with specific threshold voltages and configurations, including a latch mechanism with complementary transistors to detect the floating state without bias current, utilizing leakage currents and parasitic capacitances to maintain a stable logic level without static bias current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pull-down impedance is used to define the logic state when the switch is open, then the input state is unambiguously defined, but static current consumption increases when the switch is closed
Solution Approach 1:
The patent employs dynamic voltage thresholds through the use of transistors M2 and M3 that adjust the reference voltage level based on the state of node N. This dynamic threshold mechanism allows the circuit to distinguish between logic states without requiring continuous static bias current, resolving the contradiction between reliable state detection and energy efficiency
Solution Approach 2:
The circuit uses the inherent leakage current of transistor M1 and the parasitic capacitance of node N to automatically maintain the logic state without external bias current. The system serves itself by utilizing its own parasitic elements rather than requiring additional power-consuming components, thus eliminating static current consumption while maintaining state definition
2Speed
If the pull-down impedance is made sufficiently low to ensure fast discharge, then the discharge speed is satisfactory, but the static current consumption increases
Solution Approach 1:
Instead of continuous bias current, the circuit employs periodic action through the dynamic switching of transistors M2 and M3 that periodically adjust the voltage at node N. This periodic voltage adjustment achieves fast state transitions without requiring continuous static current, resolving the speed-power tradeoff
Solution Approach 2:
The patent changes the voltage parameter dynamically using transistors M2 and M3 to adjust the reference level based on the state of node N. By changing voltage parameters rather than relying on fixed impedance values, the circuit achieves fast discharge speeds without the penalty of high static current consumption
3Loss of energy
If intermittent measurement is used to reduce static consumption, then current consumption decreases, but brief events between measurement phases cannot be detected
Solution Approach 1:
The patent maintains continuous monitoring capability by keeping transistor M1 in a state where its leakage current continuously charges or discharges the parasitic capacitance of node N. This continuous action, rather than intermittent measurement, ensures that brief events are immediately detected while maintaining very low power consumption
4Loss of energy
If no bias current is used, then static current consumption is reduced, but the floating state cannot be properly detected
Solution Approach 1:
The patent introduces transistor M2 as an intermediary element that mediates between node N and the rest of the circuit. This intermediary transistor, along with M3, creates a voltage comparison mechanism that enables floating state detection without requiring continuous bias current, thus resolving the detection difficulty while maintaining low power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces static current consumption by leveraging leakage currents and parasitic capacitances to maintain a stable logic level, allowing for efficient detection of floating states without continuous bias current, especially suitable for low-power applications.
Implementation Method 1
discharging the node to a second voltage by a leakage current of a first MOS transistor in an off state
Implementation Method 2
utilizing leakage currents and parasitic capacitances to maintain a stable logic level without static bias current
Data Source
AI summary
The invention relates to a floating state detection circuit of a node, comprising a first conductivity type MOS transistor (M1) connected between the node (N) and a first power supply line (Vss); and a second MOS transistor (M2) of conductivity type complementary to the first conductivity type, controlled by the node (N) and connected between the gate of the first transistor (M1) and a second supply line (Vdd). In addition, a third MOS transistor (M3) of the first conductivity type connected between the gate of the first transistor (M1) and the first supply line (Vss) may be controlled by the node (N).