Floating-Input D Flip-Flop Topology for Low-Voltage High-Speed Operation
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Solution Overview
Problem
Conventional D flip-flop circuits face challenges in achieving high-speed operation at low voltages due to increased power consumption from short circuit and DC currents, limiting their frequency performance and efficiency in handheld electronic devices.
Innovation Solution
The dynamic floating input D flip-flop (DFIDFF) incorporates a floating input stage and two strings of transistors, where the floating input stage transmits input data to the first string during pre-charge and the second string determines the output level based on the first string's logic status during evaluation, reducing power consumption by minimizing short circuit and DC currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional D flip-flop circuits operate at low voltage, then power consumption is reduced, but operating frequency decreases
Solution Approach 1:
The patent employs dynamic circuit operation with pre-charge and evaluate phases controlled by clock signals. The circuit transitions between different operational states dynamically, allowing it to achieve high-speed operation during evaluation while consuming minimal power during pre-charge phases at low voltages
Solution Approach 2:
The D flip-flop operates in periodic cycles consisting of pre-charge phase and evaluate phase. During pre-charge, nodes are prepared and power consumption is minimized. During evaluate, the circuit performs high-speed operation. This periodic switching enables the circuit to achieve high average operating frequency while maintaining low overall power consumption at low supply voltages
2Speed
If conventional D flip-flop circuits operate at high speed, then operating frequency increases, but power consumption from short circuit and DC currents increases
Solution Approach 1:
The patent extracts and eliminates the harmful short circuit current paths and DC current paths from the conventional D flip-flop circuit. By redesigning the transistor configuration and adding control mechanisms, the circuit removes the sources of excessive power consumption while preserving high-speed operation capabilities
Solution Approach 2:
The patent changes the operational parameters of the circuit by introducing controlled high-impedance states during pre-charge phases. This parameter change effectively reduces current flow and power consumption during non-evaluation periods, allowing the circuit to achieve high operating frequencies only when necessary, thereby reducing overall power consumption
3Reliability
If the number of MOS transistors connected in series is increased, then circuit functionality is improved, but operating speed decreases
Solution Approach 1:
The patent segments the D flip-flop circuit into distinct functional modules: pre-charge circuitry, evaluation circuitry, and output circuitry. Each segment is optimized independently, allowing complex functionality to be achieved while minimizing the series transistor count in critical signal paths to maintain high operating speed
Data Source
AI summary
A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.