Floating Inverter Latch Comparator for Common-Mode Stability
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Solution Overview
Problem
Conventional dynamic comparator architectures are highly sensitive to input common-mode voltage, affecting performance parameters such as input-referred noise, offset, energy per comparison, and decision time, which is particularly problematic for Successive-Approximation Register (SAR) Analog-to-Digital Converters (ADCs).
Innovation Solution
A single-stage comparator architecture with a self-quenching mechanism and a floating inverter amplifier (FIA) that incorporates a latch, making it insensitive to input common-mode voltage variations, eliminating the need for separate logic elements to control capacitor discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional dynamic comparator architectures are used, then the comparator can operate with simple circuit implementation, but the performance parameters (input-referred noise, offset, energy per comparison, decision time) are adversely affected by sensitivity to input common-mode voltage
Solution Approach 1:
The patent changes the operating parameters of the comparator by introducing a floating inverter amplifier architecture where the common-mode voltage at the input transistors is decoupled from the decision node. This is achieved by using a reservoir capacitor that maintains a stable reference voltage while allowing the input common-mode to vary, thereby changing the voltage distribution parameters to achieve insensitivity to common-mode variations
Solution Approach 2:
The reservoir capacitor acts as an intermediary element between the input stage and the decision node. It mediates the voltage variations by absorbing common-mode fluctuations while maintaining a stable voltage at the latch input, thus isolating the decision mechanism from harmful common-mode variations
2Reliability
If two-stage comparator architecture is used to reduce sensitivity to common-mode voltage, then performance stability improves, but unwanted delays, complexity, and size increase
Solution Approach 1:
The patent merges the amplification and latching functions into a single integrated stage. The floating inverter amplifier simultaneously performs signal amplification and feeds the latch, eliminating the need for a separate first stage amplifier and second stage latch. This consolidation achieves common-mode insensitivity while reducing overall circuit complexity
Solution Approach 2:
The floating inverter amplifier serves multiple functions: it amplifies the differential input signal, provides common-mode rejection, and directly drives the latch circuit. This multi-functional design replaces what would traditionally require separate dedicated stages, reducing complexity while maintaining performance
3Reliability
If separate logic elements are added to control capacitor discharge in conventional comparators, then common-mode sensitivity is reduced, but device complexity and size increase
Solution Approach 1:
The reservoir capacitor automatically maintains its charging state through the inherent operation of the floating inverter amplifier. The amplifier's biasing network self-regulates to keep the capacitor charged without requiring external control logic or additional discharge control elements, achieving common-mode rejection through self-biasing mechanisms
Data Source
AI summary
A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.