Floating Lead Semiconductor Packages for Thermal Stress Reduction
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Solution Overview
Problem
Conventional multi-chip modules (MCMs) face challenges in maximizing density and minimizing thermal stress due to the concentration of heat generation, leading to issues like warpage, delamination, and electrical connection congestion, which are exacerbated by the need for thick interposers and additional wafer masks, increasing fabrication costs and time.
Innovation Solution
The solution involves positioning semiconductor devices adjacent to opposite surfaces of floating leads, allowing bond pads on one side to be connected to the leads on the other side, eliminating the need for interposers and redistributing layers, and using offset lead assemblies to balance the number of leads and accommodate an odd number of devices within a minimal thickness package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional shingle stack configuration is used with all bond pads at one edge, then electrical connection density is improved, but thermal stress concentration and warpage increase
Solution Approach 1:
The patent segments the bond pads into two groups: first bond pads located at a first edge of the semiconductor device and second bond pads located at a second edge opposite the first edge. This segmentation distributes the electrical connections and heat generation across different edges, preventing thermal stress concentration while maintaining high connection density through the use of floating leads that extend across the device.
2Stability of the object's composition
If interposer or redistribution layer is added to balance leads, then lead balance is improved, but package thickness increases
Solution Approach 1:
The patent uses floating leads that extend horizontally across the semiconductor device from one edge to the opposite edge, rather than adding vertical thickness through interposers or redistribution layers. This dimensional approach allows lead balancing to be achieved in the planar dimension while maintaining minimal package thickness.
3Object-affected harmful factors
If mirror image semiconductor devices are used, then thermal stress distribution is improved, but fabrication complexity increases
Solution Approach 1:
The patent employs asymmetric placement of bond pads on the same semiconductor device, with first bond pads at one edge and second bond pads at the opposite edge. This asymmetric configuration achieves thermal stress distribution benefits without requiring multiple mirror image devices, thereby simplifying fabrication compared to approaches that use symmetric mirror image arrangements.
4Productivity
If bond pads are located at single edge, then electrical connection efficiency is improved, but thermal stress concentration increases
Solution Approach 1:
The patent segments the electrical connections by placing first bond pads at a first edge for efficient external connections and second bond pads at the opposite edge for inter-device connections. This segmentation maintains electrical connection efficiency while distributing thermal stress across different edges of the device.
Data Source
AI summary
A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package may include at least two semiconductor devices that face opposite directions from one another, with each being oriented such that bond pads thereof are at an opposite side of the assembly or package from bond pads of the other. Alternatively, an assembly or package may include a lead assembly with an internal portion, including one or more floating leads, and an external portion that are in planes that are offset relative to one another. Methods for designing lead frames, assemblies, and packages are also disclosed, as are assembly and packaging methods.