Floating Level Shifter Using CMOS Stacking for GaN DC-DC Converters
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Solution Overview
Problem
Designing a floating level shifter for high-voltage, high-frequency GaN-based DC-DC voltage converters is challenging due to incompatibility with low-voltage CMOS processes, high dV/dt issues leading to false triggers and efficiency degradation, and the need for special devices or passive components that increase area and leakage.
Innovation Solution
An all-digital floating level shifter using low-voltage CMOS devices without special devices or passives, which senses and clips the inductor switching node voltage to generate switching signals acting as ground rails for sublevel shifters, enabling high dV/dt immunity and supporting a wide range of input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If special devices or passive components are used in the floating level shifter, then high-voltage capability is achieved, but device area and leakage increase
Solution Approach 1:
The floating level shifter is divided into multiple CMOS transistors connected in series (stacked configuration), where each transistor handles a portion of the total voltage. This segmentation allows the use of standard low-voltage CMOS devices while achieving high-voltage capability, avoiding the need for special high-voltage devices that would increase area.
Solution Approach 2:
The invention changes the operating parameters of standard CMOS devices by utilizing their inherent voltage blocking capability when properly biased. By controlling the gate voltages and using the transistors in a specific stacked arrangement, standard low-voltage CMOS transistors are made to withstand high voltages, eliminating the need for specialized high-voltage components.
2Reliability
If special devices or passive components are used in the floating level shifter, then high-voltage capability is achieved, but leakage increases
Solution Approach 1:
The voltage path is segmented across multiple transistors, with each transistor experiencing only a fraction of the total voltage. This segmentation reduces the voltage stress on individual devices and minimizes leakage currents compared to using a single special high-voltage device.
Solution Approach 2:
The stacked CMOS transistors inherently provide voltage blocking and leakage control through their own transistor characteristics when properly biased. The circuit uses the natural properties of CMOS transistors (off-state leakage, gate control) to manage high-voltage operation without requiring additional leakage-control components.
3Ease of operation
If conventional level shifting methods are used, then voltage level conversion is achieved, but false triggers occur due to high dV/dt
Solution Approach 1:
The circuit performs preliminary voltage sensing and clipping at the switching node before the level shifting operation. By pre-establishing the voltage reference and controlling the timing of the level shift, the circuit prevents high dV/dt transients from causing false triggers during the voltage conversion process.
Solution Approach 2:
The invention introduces intermediate control signals and voltage references that mediate between the high-voltage switching node and the low-voltage logic. These intermediate elements isolate the sensitive level-shifting logic from direct exposure to high dV/dt transients, preventing false triggers while maintaining proper voltage conversion.
4Power
If two-stage converters are used, then voltage conversion is achieved, but power distribution losses increase
Solution Approach 1:
The invention merges the level shifting function with the power management integrated circuit (PMIC) by implementing the floating level shifter using the same CMOS process technology. This integration eliminates the need for separate two-stage converter architectures, reducing the number of power conversion stages and minimizing power distribution losses.
Data Source
AI summary
Embodiments herein relate to a voltage converter with a floating level shifter. The floating level shifter is implemented on a silicon substrate using complementary metal-oxide semiconductor (CMOS) technology while the power train is implemented on a Gallium Nitride substrate. The floating level shifter may be all-digital and avoid the use of passive devices. The floating level shifter is responsive to a voltage output from a bootstrap circuit, a voltage of a switching node of a power train and a drive voltage of the bootstrap circuit, to shift an input signal to an output signal in a charge phase of a switching cycle. The output signal drives a high-side driver for a high-side transistor of the power train, where the voltage output from the bootstrap circuit and the voltage of the switching node alternate in charge and discharge phases of the switching cycle.