Floating Multilevel Page Table Memory Allocation
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Solution Overview
Problem
Current memory mapping techniques, such as multilevel paging, face inefficiencies when allocating large amounts of memory, particularly due to the use of linked lists which result in high latency and power consumption, as they require extensive iteration and entry additions to page tables, leading to prolonged processing times.
Innovation Solution
Implementing an active multilevel page table (MPT) and a floating MPT that share a common mapping scheme, allowing the processor to efficiently add and remove page table entries to map spare memory pages, thereby avoiding the use of linked lists and reducing the time required to allocate large memory resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If linked lists are used for memory page allocation in multilevel paging, then memory mapping can be implemented, but processing time and latency increase significantly due to extensive iteration and entry additions
Solution Approach 1:
The patent pre-creates a floating multilevel page table structure with predetermined entries that can be quickly attached to the active page table. This preliminary preparation eliminates the need for extensive iteration and entry addition during memory allocation, directly resolving the contradiction between productivity and time loss.
Solution Approach 2:
The patent merges the floating page table structure with the active page table through attachment mechanisms. By combining these two table structures, the system achieves fast memory allocation without the time-consuming iteration required by linked list approaches, thus improving productivity while reducing processing time.
2Productivity
If linked lists are used for memory page allocation, then memory mapping is achieved, but power consumption increases due to prolonged processing times
Solution Approach 1:
The floating page table is pre-configured with memory page mappings before being attached to the active page table. This preliminary action reduces the processing time required during memory allocation operations, thereby decreasing power consumption while maintaining allocation efficiency.
Solution Approach 2:
The patent uses a floating page table that contains copies of necessary mapping entries. By copying pre-computed mapping information into the floating table, the system avoids repeated computation and iteration during allocation, reducing both processing time and power consumption while maintaining high productivity.
3Reliability
If traditional multilevel paging with linked lists is used, then virtual to physical address mapping is provided, but device complexity increases due to extensive iteration requirements
Solution Approach 1:
The patent segments the page table structure into an active page table and a floating page table. This segmentation allows the system to maintain reliable address mapping while reducing complexity by pre-organizing mapping entries in the floating table, eliminating the need for extensive iteration through linked lists.
Solution Approach 2:
The floating page table is prepared in advance with predetermined virtual to physical address mappings. This preliminary organization of mapping data simplifies the active page table structure and reduces the complexity of iteration requirements, while maintaining accurate address mapping through the pre-configured entries.
Data Source
AI summary
In one embodiment, a processing device includes a memory to store a plurality of memory pages having corresponding physical memory addresses in the memory, store an active multilevel page table (MPT) mapping virtual to physical memory addresses for corresponding allocated memory pages stored in the memory, and store a floating MPT at least partially mapping virtual to physical memory addresses for corresponding spare memory pages stored in the memory, the floating and active MPT using a common mapping scheme, and a processor to receive a request to add a virtual to physical address mapping for more memory pages of the plurality of memory pages to the active MPT, and in response to receiving the request, adjoin at least part of the floating MPT to the active MPT so that the active MPT provides the virtual to physical address mapping for at least some memory pages of the spare memory pages.