Floating Node Biasing via Leakage Transistor Without Data Interrupt
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Solution Overview
Problem
Existing biasing techniques for floating nodes in semiconductor chips consume significant power and introduce complexity, particularly in proximity communication systems where direct chip-to-chip capacitive coupling blocks DC signal transmission and requires frequent refreshing or stopping data transmission.
Innovation Solution
A low-power biasing system using a four-terminal transistor, such as NMOS or PMOS, where the leakage current between selected and unselected terminals gradually biases the floating node to the desired voltage without interrupting data transmission, utilizing the transistor's cutoff mode to minimize power consumption and eliminate the need for complex refreshing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic precharging/postcharging is used to bias the floating node, then the bias voltage is maintained, but power consumption increases substantially
Solution Approach 1:
The patent applies periodic action by using a leakage transistor that periodically refreshes the floating node bias voltage through its natural leakage current, replacing the need for frequent active precharging/postcharging operations. This periodic leakage-based refreshing maintains the bias voltage while consuming significantly less power than continuous or frequent active refreshing schemes.
Solution Approach 2:
The leakage transistor serves itself by utilizing its own inherent leakage current to maintain the bias voltage on the floating node. This self-service mechanism eliminates the need for external control circuits or additional power-consuming refreshing operations, as the transistor's natural leakage property is harnessed to perform the biasing function autonomously.
2Reliability
If data transmission is stopped to refresh inputs, then biasing can be performed, but communication time increases substantially
Solution Approach 1:
The patent enables continuous data transmission while maintaining proper biasing by using the leakage transistor to continuously or periodically refresh the floating node during normal operation. This eliminates the need to stop data transmission for refreshing, as the leakage current operates concurrently with data communication, maintaining both reliability and time efficiency.
Solution Approach 2:
The leakage transistor acts as an intermediary element that simultaneously handles both the biasing function and allows data transmission to proceed uninterrupted. By positioning the leakage transistor as a parallel path or integrated component, it mediates between the need for input refreshing and the requirement for continuous communication, satisfying both demands without conflict.
3Reliability
If negative feedback from output is used to bias input, then bias voltage is established, but design complexity and power consumption increase
Solution Approach 1:
The patent extracts and utilizes the natural leakage current property of the transistor itself to establish the bias voltage, removing the need for complex negative feedback circuits. By taking out the biasing function from the main data path and using the transistor's inherent leakage characteristic, the design achieves bias voltage establishment with minimal additional complexity.
Solution Approach 2:
The transistor serves itself by using its own leakage current to establish and maintain the bias voltage on the floating node, eliminating the need for external negative feedback control circuits. This self-service approach simplifies the overall design by removing complex biasing infrastructure while maintaining reliable voltage establishment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient, low-power biasing of floating nodes with self-recovery properties, maintaining the desired bias voltage without stopping data transmission and reducing design complexity, while using a leakage current that is significantly smaller than typical conducting currents.
Implementation Method 1
the leakage current between the selected terminals and the unselected terminals is substantially smaller than a normal conducting current
Implementation Method 2
direct chip-to-chip capacitive coupling blocks DC signal transmission
Data Source
AI summary
One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.