Floating N-Well I/O Circuit for High-Voltage Leakage Isolation
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Solution Overview
Problem
Conventional input/output (I/O) circuits are vulnerable to exceeding voltage input signals, which can cause undesirable leakage currents and breakdown phenomena, leading to reliability and performance issues.
Innovation Solution
The implementation of voltage tolerant I/O circuits that include a drain-source leakage path inhibitor and a drain-bulk leakage path inhibitor, utilizing a Floating N-well Generator circuit to isolate the voltage supply from leakage currents through both drain-source and drain-bulk connections, thereby mitigating leakage currents during input mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional I/O circuits are used to interface with external circuits operating at higher voltages, then the I/O circuit can provide electrical isolation between internal and external circuitry, but the I/O circuit becomes vulnerable to exceeding voltage input signals causing leakage currents and breakdown phenomena
Solution Approach 1:
The patent introduces a floating n-well structure as an intermediary element between the p-channel transistor and the external high-voltage circuitry. This floating n-well acts as a mediator that captures and isolates excessive voltage, preventing it from reaching the voltage supply and causing harmful leakage currents or breakdown. The n-well is connected to a high-impedance node that allows it to float at the voltage level of external circuitry without conducting harmful currents.
Solution Approach 2:
The patent changes the electrical parameters of the transistor structure by implementing a floating n-well configuration. This modifies the voltage distribution and electrical characteristics of the p-channel transistor, enabling it to tolerate input voltages exceeding the supply voltage without entering breakdown or generating excessive leakage currents. The floating n-well alters the electric field distribution and potential barriers within the transistor.
2Adaptability or versatility
If the I/O circuit is designed to accept exceeding voltage input signals, then voltage tolerance is improved, but leakage currents increase and cause detrimental effects on internal circuitry
Solution Approach 1:
The floating n-well serves as an intermediary that intercepts excessive voltage before it can flow into the voltage supply through the p-channel transistor. By placing the n-well between the external circuitry and the transistor channel, it mediates the voltage interaction, allowing the circuit to accept high-voltage inputs while preventing harmful leakage currents from reaching sensitive internal circuitry.
Solution Approach 2:
The patent extracts the harmful leakage current path by introducing the floating n-well structure that separates the high-voltage input path from the voltage supply. This extraction removes the direct leakage path that would otherwise exist through the transistor's drain-bulk junction, isolating the harmful effects from the internal circuitry.
3Device complexity
If conventional transistor structures are used in the I/O circuit, then device complexity is reduced, but the transistors become electrically over-stressed when exposed to exceeding voltage input signals
Solution Approach 1:
The patent modifies the transistor structure parameters by adding a floating n-well region to conventional p-channel transistors. This structural parameter change enables the transistors to withstand voltage stresses that would otherwise cause breakdown or excessive leakage. The floating n-well creates additional potential barriers and modifies the electric field distribution, allowing the transistors to operate reliably with input voltages exceeding the supply voltage without requiring fundamentally new device architectures.
Data Source
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AI summary
Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.