Floating N-Well Bias Circuit for Low DVDD Voltage Detection
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Solution Overview
Problem
Existing floating N-well bias circuits are limited in providing N-well bias voltage when the voltage difference between the first power (VDD) and the second power (DVDD) is less than a threshold voltage, leading to a situation where the N-well bias voltage can only be provided when the voltage difference is greater than the threshold.
Innovation Solution
A low-voltage detection floating N-well bias circuit is designed with a power detector, a switch, and a voltage output circuit. The circuit detects the states of the first and second powers and switches between them to output either the first or second power as an N-well bias voltage, ensuring continuous biasing without dropping the second power, even when it is in a low voltage state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional floating N-well bias circuit is used, then the N-well bias voltage can be provided when the voltage difference between VDD and DVDD is greater than the threshold voltage, but the N-well bias voltage cannot be provided when the voltage difference is less than the threshold voltage or when DVDD is in a low voltage state
Solution Approach 1:
The circuit dynamically switches between different PMOS transistors (MP1, MP2, MP3) based on the voltage states of VDD and DVDD. The power detector continuously monitors the voltage levels and controls the switching elements to adapt the biasing configuration in real-time, enabling reliable N-well biasing across varying voltage conditions including low voltage states where conventional circuits fail.
Solution Approach 2:
A power detector is introduced as an intermediary component that monitors the voltage states of VDD and DVDD and controls the switching elements accordingly. This intermediary enables the circuit to detect low voltage conditions and activate appropriate biasing paths that would otherwise remain inactive in conventional circuits, extending the operating range.
2Reliability
If the voltage difference between VDD and DVDD is less than the threshold voltage, then the second PMOS transistor (MP2) turns off, but this prevents the N-well bias voltage from being provided
Solution Approach 1:
The power detector performs preliminary detection of the voltage states before the biasing operation. When DVDD is detected to be in a low voltage state or when the voltage difference is insufficient, the detector proactively activates alternative biasing paths through controlled switching, preventing the bias voltage from dropping and ensuring continuous N-well biasing without requiring a minimum voltage difference.
Solution Approach 2:
The circuit changes the operational parameters by switching between different PMOS transistors with different gate voltage requirements. When MP2 cannot conduct due to insufficient voltage difference, the switching element activates MP3 which can provide the necessary bias voltage under different voltage conditions, effectively changing which transistor parameter set is active based on the input voltage states.
3Speed
If a simple bias circuit configuration is used, then the circuit structure remains simple, but the circuit cannot respond quickly to rapid changes in external or internal supply power
Solution Approach 1:
The bias circuit is segmented into distinct functional modules: a power detector module that monitors voltage states, switching elements (MP1, MP2, MP3) that can be independently controlled, and connection structures that link these modules. This segmentation allows each module to operate independently and respond quickly to power changes, improving overall response speed while keeping each individual module relatively simple.
Data Source
AI summary
Disclosed is a low-voltage detection floating N-well bias circuit. The circuit includes a power detector configured to detect states of first power (VDD) and second power (DVDD) at different power levels; a switch configured to perform a switching operation according to the states of the first power (VDD) and the second power (DVDD); and a voltage output circuit configured to output the first power (VDD) or the second power (DVDD) as an N-well bias voltage according to the states of the first power (VDD) and the second power (DVDD) and the switching operation of the switch. Accordingly, when the first power (VDD) and the second power (DVDD) are supplied and the second power (DVDD) has a low voltage state, the floating N-well bias circuit can continuously bias an N-well with the second power (DVDD), without dropping the second power (DVDD).