Floating N-Well I/O Circuit With Pull-Down Leakage Inhibition
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Solution Overview
Problem
Conventional input/output circuits are vulnerable to exceeding voltage input signals, leading to undesirable leakage currents and breakdown phenomena, which can compromise their reliability and performance.
Innovation Solution
The implementation of voltage tolerant floating N-well circuits, which include a driver circuit with a controllable pull-down path and a leakage path inhibitor to isolate leakage currents through drain-source and drain-bulk connections, mitigating the effects of exceeding voltage input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional I/O circuits are used to interface with external circuits operating at higher voltages, then the circuit can provide basic electrical interface functionality, but leakage currents and breakdown phenomena occur when input voltages exceed the supply voltage
Solution Approach 1:
A floating N-well structure is introduced as an intermediary between the external high-voltage input signal and the internal circuit components. The N-well acts as a protective barrier that captures and isolates excess voltage, preventing it from reaching and damaging sensitive transistors and oxide layers while allowing the circuit to interface with higher voltage external devices
2Adaptability or versatility
If the I/O circuit accepts exceeding voltage input signals to interface with a wide variety of peripherals, then adaptability is improved, but leakage currents increase and breakdown phenomena occur
Solution Approach 1:
The floating N-well structure is configured to preemptively absorb and isolate exceeding voltage inputs before they can cause harmful leakage currents. By establishing this protective structure in advance, the circuit can safely accommodate a wide range of peripheral voltage levels without experiencing the detrimental leakage effects that would otherwise occur
Data Source
AI summary
Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.