Floating-Point Hardware Accelerator Using Mantissa Segmentation
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Solution Overview
Problem
Machine-learning models, particularly convolutional neural networks, face performance challenges in floating-point multiplication operations due to the complexity and slowness of these operations compared to integer operations, which can lead to accuracy loss when using lower-precision floating-point data types or increased costs and power usage with additional hardware resources.
Innovation Solution
A hardware accelerator that improves floating-point multiplication performance by dividing the mantissas of floating-point data elements into portions and reducing the number of multiplication operations by excluding the least-significant bits, thereby maintaining precision with minimal impact on accuracy, and utilizing integer multiplier circuits to perform these operations in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point multiplication operations are performed using conventional hardware, then accuracy is maintained, but operation speed is slow and complexity is high
Solution Approach 1:
The patent divides the mantissa of floating-point numbers into multiple segments (e.g., high-order and low-order segments). Integer multiplier circuits process these segments separately and in parallel, then combine the results to produce the final product. This segmentation enables parallel processing while maintaining full precision, resolving the contradiction between speed and accuracy.
2Productivity
If additional hardware resources are added to improve floating-point multiplication performance, then operation speed increases, but manufacturing cost and power usage increase
Solution Approach 1:
The patent replaces complex floating-point multiplication hardware with simpler integer multiplication circuits. By treating floating-point mantissas as integers for the multiplication operation and handling the fractional nature through segmentation and combination, the design uses less complex, more cost-effective hardware while achieving high-speed operation.
3Productivity
If additional hardware resources are added to improve floating-point multiplication performance, then operation speed increases, but power usage increases
Solution Approach 1:
The patent substitutes power-intensive floating-point multiplication circuits with more energy-efficient integer multiplication circuits. The segmented approach allows parallel processing using simpler logic gates that consume less power, while still delivering high-speed results through the parallel combination of partial products.
4Productivity
If lower-precision floating-point data types are used to improve operation speed, then processing time decreases, but accuracy is lost
Solution Approach 1:
The patent segments the mantissa into multiple parts that are processed in parallel by integer multipliers. By maintaining all significant bits through this segmented parallel processing approach, the system achieves both high speed and full precision, eliminating the need to trade accuracy for speed that characterizes lower-precision formats.
Data Source
AI summary
A device includes integer multiplier circuits, a multiplexer circuit configured to provide portions of mantissas of a set of first data elements having a floating-point data type and portions of mantissas of a set of second data elements having the floating-point data type to respective integer multiplier circuits, wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element to generate a partial product. The device further includes output circuits configured to generate an output data element based on the partial products generated by the integer multiplier circuits and exponents of the set of first data elements and of the set of second data elements. The multiplexer circuit is further configured to bypass providing least-significant portions of the mantissas of the set of first data elements to integer multiplier circuits for multiplication with least-significant portions of the mantissas of the set of second data elements.