Floating-Point Adder Circuit for AI Accelerator Latency Reduction
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Solution Overview
Problem
Deep learning applications face performance degradation due to limitations in data communication between separate memory and processor units, leading to inefficiencies in neural network computations, particularly in artificial intelligence systems.
Innovation Solution
An adder circuit with a negative number processing circuit and an adder tree is introduced, capable of processing mantissa data and sign data for floating-point operations, optimizing addition operations by inverting mantissa data for negative signs and performing operations with an appropriate number of '+1' operations, integrated within a processing-in-memory (PIM) device to enhance data processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If floating-point addition operations are performed using conventional methods in separate processor units, then computational accuracy is maintained, but data communication limitations between memory and processor degrade AI performance
Solution Approach 1:
The patent merges the memory unit and processor unit into a single integrated device, allowing floating-point addition operations to be performed directly within the memory unit. This eliminates the need for data communication between separate memory and processor units, thereby improving AI computation performance and reducing communication time.
Solution Approach 2:
The patent introduces a dedicated floating-point addition circuit as an intermediary component within the memory unit. This circuit enables direct computation on stored data without requiring external processor intervention, effectively bridging the gap between memory storage and computational processing.
2Measurement precision
If the number of layers in neural networks is increased to improve AI performance, then computational accuracy improves, but the amount of computation required increases exponentially
Solution Approach 1:
The patent segments the computation process by implementing dedicated floating-point addition circuits within memory units. This segmentation allows computation to be distributed across multiple memory units rather than concentrated in a single processor, reducing the computational burden on individual units and enabling handling of more complex neural networks.
3Adaptability or versatility
If general hardware systems with separate memory and processor are used, then system flexibility is maintained, but data communication limitations degrade AI performance
Solution Approach 1:
The patent implements a universal floating-point addition circuit within the memory unit that can handle various floating-point operations. This multi-functional circuit maintains system flexibility while enabling direct computation on stored data, thereby improving data processing speed without sacrificing adaptability.
Data Source
AI summary
An adder circuit includes a negative number processing circuit configured to receive mantissa data and sign data of a plurality of floating point data and configured to output selected mantissa data, and an adder tree configured to perform an addition operation on the selected mantissa data to generate mantissa addition data. The negative number processing circuit is configured to output mantissa data of floating point data having a positive sign as the selected mantissa data, and to output an inverted mantissa data in which values of mantissa data of the floating point data having a negative sign are inverted as the selected mantissa data. And the adder tree is configured to perform the addition operation on the selected mantissa data with a number of “+1” operations equal to the number of the inverted mantissa data output from the negative number processing circuit.