Floating-Point Adder Denormal Handling Far Close Path Circuits
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Solution Overview
Problem
Existing floating-point addition units struggle with performance when handling denormal numbers, leading to significant computational delays and inefficiencies, as they often require separate hardware units and result in slower processing speeds compared to normal number operations.
Innovation Solution
A floating-point addition unit is designed with a far path circuit and a close path circuit, along with a final result selector, to handle both normal and denormal numbers efficiently, allowing for parallel processing and accurate computation without the need for separate hardware units, by adjusting exponent portions and radix shifting accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate hardware units are used for denormal number operations, then denormal number processing capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the handling of both normal and denormal numbers into a single floating-point addition unit. The unified structure uses conditional logic within the same hardware to detect whether operands are normal or denormal and applies appropriate processing paths, eliminating the need for separate hardware units while maintaining full functionality.
Solution Approach 2:
The floating-point addition unit is designed as a universal circuit that can handle both normal and denormal number operations. The unit incorporates detection mechanisms that identify the type of operands and automatically select the appropriate processing mode, making the same hardware structure multi-functional rather than requiring dedicated separate units.
2Measurement precision
If separate hardware units are used for denormal numbers, then processing accuracy for denormal numbers is improved, but processing speed deteriorates
Solution Approach 1:
The patent implements preliminary detection of operand types (normal vs. denormal) at the input stage of the floating-point addition unit. This early identification allows the circuit to prepare and select the appropriate processing path in advance, avoiding delays that would occur if denormal detection and handling were performed sequentially after normal processing.
Solution Approach 2:
The processing path within the unified hardware unit dynamically adapts based on the detected operand types. The circuit automatically switches between different processing modes (normal number processing, denormal number processing, or mixed processing) without requiring external control signals or sequential decision-making, enabling parallel path selection that maintains high processing speed while ensuring accurate denormal handling.
3Speed
If standard floating-point addition unit is used without denormal support, then processing speed for normal numbers is maintained, but denormal number handling requires additional hardware
Solution Approach 1:
The patent combines the denormal number handling functionality directly into the standard floating-point addition unit structure. By integrating the detection and processing logic for denormal numbers within the existing hardware framework, the design maintains the original processing speed for normal numbers while adding denormal support without requiring completely separate hardware paths.
Data Source
AI summary
According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating point operands.