Floating-Point Adder Circuit Using Multi-Function Multiplier
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Solution Overview
Problem
The high cost and latency associated with implementing floating-point addition in Field-Programmable Gate Arrays (FPGAs) due to the expense of shifters for alignment and normalization in floating-point arithmetic, which increases complexity and reduces sample rate.
Innovation Solution
A floating-point adder circuit design that utilizes a dual-path approach with a near path and far path calculation, employing a fixed-point multiplier for exponent calculation and normalization, and a leading zero anticipation circuit to minimize the need for multi-bit shifters, allowing a single shift circuit to perform both left and right shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional shifters are used for alignment and normalization in floating-point addition, then floating-point arithmetic can be performed, but the cost and latency increase substantially
Solution Approach 1:
The patent makes the fixed-point multiplier perform multiple functions: it acts as both a multiplier and a shifter. By configuring the multiplier to perform shift operations (left shift for normalization, right shift for alignment), the system eliminates the need for separate shifters, thereby reducing device complexity while maintaining floating-point arithmetic capability
Solution Approach 2:
The patent merges the shifter functionality into the existing multiplier component. Instead of having separate dedicated shifters for alignment and normalization, the system combines these operations into the multiplier's operational modes, reducing the overall number of components and simplifying the architecture
2Measurement precision
If multi-bit shifters are used for alignment in floating-point addition, then proper alignment can be achieved, but the logic delay and sample rate reduction increase
Solution Approach 1:
The patent replaces the mechanical shift operation (which physically moves bits through dedicated shifter circuits) with a computational approach using the multiplier. The multiplier performs shift operations through mathematical multiplication by powers of two, which can be done with less logic delay than traditional bit-shifting mechanisms
Solution Approach 2:
The patent uses the leading zero anticipation circuit to predict and prepare shift operations in advance. By anticipating when shifts are needed based on the input values, the system can prepare the necessary alignment operations beforehand, reducing the overall delay and maintaining higher sample rates
3Adaptability or versatility
If floating-point adder is implemented in FPGA, then floating-point operations are available, but the cost is very high compared to fixed-point arithmetic
Solution Approach 1:
The patent makes the fixed-point multiplier serve dual purposes: performing both multiplication and shift operations. By configuring the same hardware component to handle multiple functions (multiplier mode for multiplication, shifter mode for alignment and normalization), the system achieves floating-point capability without requiring separate dedicated floating-point adder hardware, thereby reducing implementation cost
Solution Approach 2:
The system uses existing FPGA resources (the fixed-point multiplier) to perform floating-point operations. Instead of requiring expensive dedicated floating-point hardware, the patent leverages the self-service capability of the existing multiplier to handle shift operations, making the floating-point implementation cost-effective by utilizing already-present hardware resources
Data Source
AI summary
A floating-point adder circuit is described. The circuit comprises an input multiplexer coupled to receive a first input value and a second input value; an adder-subtractor circuit selectively coupled to receive one of the first input value and the second input value at each of a first input and a second input, wherein the value coupled to the second input is added to or subtracted from the value coupled to the first input; a right shift circuit for aligning the smaller of the first input value and the second input value which is coupled to the second input of the adder-subtractor circuit; and an additional shift circuit (e.g., a left shift/right shift circuit of a combined near path and far path) coupled to the output of the adder-subtractor circuit. A method of implementing a floating-point adder is also disclosed.