Floating Point Adder Near Far Path Selection Logic
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Solution Overview
Problem
Existing floating point addition techniques often require the far path for most additions, leading to increased latency and power consumption, as they lack efficient mechanisms to utilize the near path effectively.
Innovation Solution
A data processing apparatus that determines specific criteria to direct operations between near and far paths, allowing the near path to handle more additions by using first adder logic for like-signed additions requiring a 1-bit right shift and second adder logic for unlike-signed additions requiring a 1-bit left shift, with integrated logic to minimize additional cycles and logic requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the far path is used for most additions, then the addition operation can be performed with sufficient accuracy, but the latency increases and power consumption increases
Solution Approach 1:
The patent divides the floating point addition operation into two separate paths: near path and far path. The near path handles specific cases (like-signed additions requiring 1-bit right shift or unlike-signed additions requiring 1-bit left shift) with reduced latency, while the far path handles other cases with full precision. This segmentation allows the system to optimize for speed in common cases while maintaining accuracy for all cases.
Solution Approach 2:
The patent changes the operational parameters of the adder logic based on the input characteristics. By detecting specific conditions (sign combinations and required shift amounts), the system dynamically selects between near path and far path execution, effectively changing the processing parameters to match the input requirements and achieve optimal performance.
2Measurement precision
If the far path is used for most additions, then the addition operation can be performed with sufficient accuracy, but the power consumption increases
Solution Approach 1:
The patent segments the addition operation into near path and far path, where the near path consumes less power for specific common cases. By routing appropriate operations through the lower-power near path, the overall power consumption is reduced while maintaining accuracy through selective use of the far path when needed.
Solution Approach 2:
The system dynamically changes the operational mode between near path and far path based on input parameters, allowing power consumption to be adjusted according to the specific addition requirements. This parameter-based selection enables energy-efficient operation for common cases while preserving accuracy for all cases.
3Productivity
If the near path is used to handle more additions, then the processing speed increases, but the device complexity increases
Solution Approach 1:
The patent applies local quality by making the near path adder logic specialized for specific operation types (like-signed or unlike-signed additions with particular shift requirements). This localized optimization allows the near path to handle specific cases efficiently without requiring the full complexity of the far path, thereby increasing processing speed for those cases while controlling overall device complexity.
4Productivity
If criteria-based path selection is implemented, then more additions can be performed in the near path, but additional determination logic is required
Solution Approach 1:
The determination logic is locally optimized to detect specific patterns (sign combinations and exponent differences) that indicate near path applicability. By focusing the determination logic on detecting only the specific cases suitable for near path execution, the patent achieves high near path utilization without requiring complex general-purpose decision-making logic.
Data Source
AI summary
A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is the larger operand. First adder logic is used, if predetermined criteria exists, to perform an addition of the n-bit significands of the first and second floating point operands to produce the sum value, whilst second adder logic is used, if the predetermined criteria does not exist, to perform that addition. Result logic can then derive the n-bit result from either an output of the first adder logic or an output of the second adder logic. If the addition is a like-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require an effective 1-bit right shift to normalise the sum value, whereas if the addition is an unlike-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require at least an effective 1-bit left shift to normalise the sum value.