Floating Point Argument Reduction Circuitry for Rounding Control
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Solution Overview
Problem
Floating point divide operations are costly and complex in terms of circuitry and computation time, and existing techniques often compromise on accuracy to reduce performance impact.
Innovation Solution
The implementation of argument reduction circuitry with reduce and round operations to generate a modified floating point value with a truncated significand, preventing roundoff errors and enabling efficient floating point operations like division while ensuring accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If accurate floating point divide operation is performed, then computation accuracy is improved, but computation time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing argument reduction on the input operands before the main division operation. The reduce and round circuitry pre-processes the significands by truncating them to N bits shorter length and applying rounding, which prepares the data in advance to enable the argument reduction operation to proceed without introducing roundoff errors, thereby achieving both accuracy and efficiency
2Productivity
If dedicated logic circuitry is constructed to increase divide operation performance, then computation time is reduced, but device complexity and silicon area cost increase significantly
Solution Approach 1:
The patent segments the floating point division process into distinct functional components: the reduce and round circuitry that processes significands, the argument reduction circuitry that performs the main computation, and the final result generation stage. This segmentation allows each component to be optimized independently and reused for other operations, reducing overall device complexity while maintaining high divide operation performance
Solution Approach 2:
The argument reduction circuitry designed according to this patent can be reused for multiple floating point operations beyond division, such as multiplication and other transcendental functions. By making the circuitry universal and multi-functional, the patent avoids the need for dedicated logic for each operation, thereby reducing silicon area cost and device complexity while maintaining high performance
3Productivity
If techniques are used to perform floating point division with less performance impact, then computation time is reduced, but computation accuracy deteriorates due to roundoff errors
Solution Approach 1:
The patent applies preliminary anti-action by proactively preventing roundoff errors before they can occur during the argument reduction operation. The reduce and round circuitry truncates significands and applies rounding in advance, creating modified floating point values that are specifically designed to inhibit roundoff errors during subsequent operations, thereby maintaining both speed and accuracy
Data Source
AI summary
An apparatus and method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation, and in addition provides reduce and round circuitry that generates from a supplied floating point value a modified floating point value to be input to the argument reduction circuitry. The reduce and round circuitry is arranged to modify a significand of the supplied floating point value, based on a specified value N, in order to produce a truncated significand with a specified rounding applied, the truncated significand being N bits shorter than the significand of the supplied floating point value, and then being used as a significand for the modified floating point value. The specified value N is chosen such that the argument reduction operation performed using the modified floating point value will inhibit roundoff error in a result of the argument reduction operation. By enabling roundoff error to be inhibited in such a way, it is possible to use such argument reduction circuitry in the computation of a number of floating point operations while enabling the correct rounded result to be obtained.