Floating-Point Conversion Circuit Without Exponent Bias Subtraction
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Solution Overview
Problem
Existing binary logic circuits for converting floating point numbers to fixed point numbers are inefficient due to the need to subtract the exponent bias, which slows down the conversion process and increases hardware requirements.
Innovation Solution
A binary logic circuit that shifts the mantissa of a floating point number based on the exponent without subtracting the bias, using a split-path shifter or a single shifter that offsets the exponent to determine the shift value, allowing for efficient conversion in both directions (left and right) using a single shifter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the exponent bias is subtracted to convert floating point to fixed point, then the conversion is accurate, but the conversion time increases and hardware requirements increase
Solution Approach 1:
The patent extracts and eliminates the bias subtraction operation from the conversion process. By recognizing that the bias value is constant and can be pre-compensated in the shift amount, the time-consuming subtraction operation is removed entirely from the critical conversion path, while maintaining accuracy through the offset compensation mechanism.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and incorporating the bias compensation into the shift amount determination. Instead of subtracting bias during conversion, the method pre-adjusts the exponent interpretation to account for bias, so the actual conversion only requires a shift operation without subsequent correction.
2Measurement precision
If the exponent bias is subtracted to convert floating point to fixed point, then the conversion is accurate, but the hardware requirements increase
Solution Approach 1:
The patent removes the subtraction unit from the hardware architecture by extracting the bias compensation logic into the shift amount calculation. This eliminates the need for dedicated subtraction circuitry while preserving conversion accuracy through the modified exponent interpretation method.
Solution Approach 2:
The patent substitutes the mechanical subtraction operation with a logical shift operation. By changing the computational approach from arithmetic subtraction to bit-shifting based on pre-compensated exponent values, the hardware complexity is reduced while maintaining the same functional outcome.
3Device complexity
If a single shifter is used instead of split-path shifter, then the hardware requirements are reduced, but the ability to handle both left and right shifts efficiently may be compromised
Solution Approach 1:
The patent makes the single shifter universal by designing it to handle both left and right shifts through a unified control mechanism. The shifter is configured to interpret the shift amount and direction from the pre-compensated exponent value, allowing it to perform both left-shifts (for positive exponents) and right-shifts (for negative exponents) using the same hardware unit.
Solution Approach 2:
The patent changes the parameter interpretation of the exponent to enable a single shifter to handle bidirectional operations. By modifying how the exponent value is used (as a direct shift amount with implicit direction based on sign), the same shifter hardware can efficiently perform both left and right shifts without requiring separate dedicated units.
Data Source
AI summary
A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes an offset unit configured to offset the exponent of the floating point number by an offset value equal to (iw−1−sy) to generate a shift value sv of sw bits given by sv=(B−E)+(iw−1−sy), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format; a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the shifter being configured to right-shift the input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2ew-1−1, iw−1−sy)+min(2ew-1−2, fw)]≤k≤sw, where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number.