Floating Point Circuit Division via Transform Factors

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Solution Overview

Problem

Existing floating point operation circuits require dedicated hardware accelerators for division operations, which are costly, area-intensive, and lack flexibility, limiting their implementation in applications with space and budget constraints.

Innovation Solution

A method and integrated circuit that utilize a floating point operation circuit capable of performing fused multiplication and addition operations to also support division operations by generating a transform factor and simplified values, allowing for efficient division calculations without the need for a separate hardware accelerator.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a dedicated hardware accelerator is implemented for division operations, then division speed is improved, but area and cost increase

Engineering Contradiction:

Improvedivision speedVSAvoidcircuit area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The floating point operation circuit is designed to perform multiple functions including fused multiplication and addition operations, as well as division operations through software control. The same hardware resources are utilized for different mathematical operations, eliminating the need for dedicated division hardware while maintaining division capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of implementing a physical hardware accelerator for division, the patent uses software instructions that replicate the division functionality through algorithmic computation using the existing floating point operation circuit. The division operation is copied as a software process rather than being implemented as separate hardware.

Inventive Principle:

Principle #26Copying

2Speed

If a dedicated hardware accelerator is implemented for division operations, then division speed is improved, but flexibility decreases

Engineering Contradiction:

Improvedivision speedVSAvoidoperational flexibility

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The floating point operation circuit operates in different modes (first operation mode for fused multiplication and addition, second operation mode for division) that can be dynamically switched through software instructions. This dynamic reconfigurability allows the same hardware to adapt to different computational needs, maintaining high flexibility while achieving fast division performance.

Inventive Principle:

Principle #15Dynamics

3Speed

If a dedicated hardware accelerator is implemented for division operations, then division speed is improved, but cost increases

Engineering Contradiction:

Improvedivision speedVSAvoidmanufacturing cost

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The circuit design achieves multi-functionality by enabling the floating point operation circuit to perform both fused multiplication and addition operations and division operations. This eliminates the need for manufacturing separate dedicated division hardware, reducing production costs while maintaining division capability through software-controlled operation modes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230004349A1Operating method of floating point operation circuit and integrated circuit including floating point operation circuit

Publication Date: 2023.01.05 SAMSUNG ELECTRONICS CO LTD

AI summary

An operating method of a floating point operation circuit includes, in response to receiving a first instruction, generating a first output by performing a fused multiplication and addition operation on a first input, a second input, and a third input. The method further includes, in response to receiving a second instruction, generating a second output by inverting one input of a fourth input, a fifth input, and a sixth input. Generating the second output includes generating a transform factor and a simplified value from the one input.