Floating Point Division Circuit Iterative Subtraction
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Solution Overview
Problem
Modern processors face challenges in determining the exact time required to complete division operations, leading to indeterminate length algorithms and idle instruction stacks, especially during floating-point division.
Innovation Solution
A division circuit is designed with a first normalizer to shift the dividend to a higher power, a second normalizer to shift the divisor, and a subtraction circuit to iteratively subtract the divisor from the dividend for a number of iterations based on the shifts, allowing for precise determination of the number of clock cycles required for the division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional division algorithms are used, then division operations can be performed, but the processor cannot predict when the division will be complete, causing the core to idle
Solution Approach 1:
The patent calculates the number of iterations required for division before the actual division operation begins. By determining the iteration count in advance based on input values and circuit configuration, the system knows exactly how long the division will take, allowing the core to execute other instructions during the division process without idling.
2Productivity
If multiplication circuits replace division circuits, then division problems are transformed into multiplication problems, but the indeterminate length algorithm issue persists
Solution Approach 1:
The division operation is segmented into discrete iterative steps where the dividend is repeatedly subtracted by the divisor. Each iteration produces a quotient bit, and the process continues for a predetermined number of iterations. This segmentation allows the circuit to perform division through simple, predictable operations rather than complex continuous algorithms.
Solution Approach 2:
The patent uses normalizers to shift inputs to higher powers and a denormalizer to shift the result to a lower power, changing the scale parameters of the numbers involved. This parameter transformation enables the division circuit to work with normalized values, simplifying the iteration process and allowing predictable completion time while maintaining accuracy.
3Reliability
If the core waits for division completion, then accurate results are obtained, but other computational resources remain idle during the division operation
Solution Approach 1:
The patent enables continuous useful action by allowing the processor core to execute other instructions during the division operation. Since the number of iterations is predetermined, the core can seamlessly switch to other tasks without waiting for division completion, ensuring continuous productive use of computational resources while maintaining division accuracy through the structured iterative process.
Data Source
AI summary
A division circuit including a first normalizer configured to shift a first input to a first higher power; a second normalizer configured to shift a second input to a second higher power; a subtraction circuit configured to iteratively subtract the second input from the first input for a number of iterations to produce a result, the number of iterations based on a number of shifts of the first input; a first output configured to provide the result; and a second output configured to provide the number of iterations.