Floating Point Representation Using Fixed-Point Registers
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Solution Overview
Problem
Existing signal processing systems face a tradeoff between computing accuracy and efficiency, with high numerical precision requiring complex representations that increase hardware costs and power consumption, particularly in performing complex number floating-point operations.
Innovation Solution
A computer-implemented method and system that utilizes a floating-point representation with a common exponent for real and imaginary components, split between fixed-point registers, and employs lazy normalization and denormalization techniques to simplify multiply-add operations, reducing the need for frequent exponent comparisons and shifts, thereby improving computing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If IEEE 754 floating point representation is used to maintain high numerical precision, then computing accuracy is improved, but hardware cost and power consumption increase
Solution Approach 1:
The floating point number is segmented into two separate registers: a fraction field register storing the mantissa and an exponent field register storing the exponent. This segmentation allows the system to handle floating point operations using simpler fixed point arithmetic units while maintaining floating point precision, thereby reducing hardware complexity and cost.
Solution Approach 2:
The patent introduces an intermediary representation where floating point numbers are stored as separate fraction and exponent fields in fixed point registers. This intermediary form enables the use of simpler fixed point arithmetic logic to perform operations that would traditionally require complex floating point units, reducing hardware cost while maintaining precision.
2Measurement precision
If IEEE 754 floating point representation is used to maintain high numerical precision, then computing accuracy is improved, but power consumption increases
Solution Approach 1:
By segmenting the floating point representation into separate fraction and exponent fields stored in fixed point registers, the system avoids the need for power-consuming floating point arithmetic logic. The segmentation enables use of lower-power fixed point arithmetic units while maintaining floating point precision through software-managed exponent manipulation.
Solution Approach 2:
The intermediary fixed point representation with separate exponent fields serves as a power-efficient mediator. It allows arithmetic operations to be performed using low-power fixed point units while the exponent information is preserved and manipulated separately to maintain floating point precision, significantly reducing power consumption compared to traditional floating point units.
3Measurement precision
If complex floating point operations are performed with frequent normalization and denormalization, then numerical precision is maintained, but computing efficiency decreases
Solution Approach 1:
The system performs preliminary normalization by maintaining the exponent field separately and adjusting it proactively during arithmetic operations. Instead of waiting for overflow or underflow conditions, the exponent is pre-adjusted based on the operation type (addition, subtraction, multiplication, division), reducing the need for frequent normalization cycles and improving computing efficiency.
Solution Approach 2:
The exponent information is extracted from the traditional floating point representation and stored separately in a dedicated exponent field register. This extraction allows the fraction field to be manipulated using simple fixed point arithmetic without the overhead of concurrent exponent management, significantly improving computing efficiency while maintaining precision through separate exponent tracking.
Data Source
AI summary
A computer implemented method for performing floating point operations as part of a processor architecture that also includes fixed point operations is disclosed. The computer implemented method includes providing a group of instructions within the fixed point architecture. A floating point value is split between two programmer visible registers. In a system and method in accordance with the present invention a new form of floating point representation and associated processor operations, including efficient complex number representations and operations are utilized.