Floating-Point Precision Power Reduction via Gating Signals
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Solution Overview
Problem
Current integrated circuits face high power consumption and area costs due to compliance with IEEE 754 Standard for floating-point operations, which is unnecessary for computations not requiring full precision and rounding compliance.
Innovation Solution
A method that reduces power consumption by using partial precision in floating-point operations through a fused multiply-add instruction, where gating signals are generated to turn off logic gates based on the low-order bits of operands, allowing for trade-offs between precision and power savings based on the relative differences in exponents of the operands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full IEEE 754 Standard compliance is implemented for floating-point operations, then precision and rounding compliance are improved, but power consumption and area cost increase
Solution Approach 1:
The patent applies partial precision computation by determining which low-order bits of operands can be ignored based on exponent differences. When the exponent difference exceeds a threshold, the method selectively disables computation of certain bit positions in the result, performing only the necessary portion of the calculation required for the given precision level rather than always computing all bits
Solution Approach 2:
The patent changes the precision parameter dynamically based on input characteristics. By analyzing the exponents of input operands and calculating the required result precision, the system adjusts the number of significant bits to compute, transforming from a fixed-precision approach to a variable-precision approach that adapts to the specific computational requirements
2Reliability
If full IEEE 754 Standard compliance is implemented for floating-point operations, then rounding compliance is improved, but area cost increases
Solution Approach 1:
The patent performs only the necessary rounding operations required for the actual precision needed. By determining the significant bit positions based on exponent differences and selectively computing only up to that precision level, the method avoids implementing full rounding logic for all possible bit positions, thereby reducing the area required for rounding compliance circuitry
3Measurement precision
If low-order bits are fully computed in floating-point operations, then precision is improved, but power consumption increases due to more flip-flop switches
Solution Approach 1:
The patent extracts and identifies the low-order bits that can be safely ignored based on exponent analysis. By separating the significant bits from the insignificant low-order bits, the method removes the unnecessary computation and associated flip-flop switching activity, thereby reducing dynamic power consumption while maintaining the required precision
Data Source
AI summary
An approach is provided for enabling power reduction in floating-point operations. In one example, a system receives floating-point numbers of a fused multiply-add instruction. The system determines the fused multiply-add instruction does not require compliance with a standard of precision for floating-point numbers. The system generates gating signals for an integrated circuit that is configured to perform operations of the fused multiply-add instruction. The system then sends the gating signals to the integrated circuit to turn off a plurality of logic gates included in the integrated circuit.