Floating-Point Multiplier Implied-Bit Handling for Parallel Execution
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Solution Overview
Problem
Digital signal processors face challenges in handling real-time data processing due to memory bandwidth limitations and scheduling constraints, particularly in applications requiring predictable non-sequential input patterns for video encoding and other data streams.
Innovation Solution
The implementation of a streaming engine within the DSP core that manages data streams by generating addresses, performing data formatting, and providing formatted data to the processor, allowing for parallel processing of implied bits during floating-point multiplication operations, thereby enhancing memory bandwidth and reducing cache miss stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sequential processing of floating-point multiplication is used, then processing accuracy is maintained, but processing speed decreases due to serial execution of implied bit determination and multiplication operations
Solution Approach 1:
The patent determines the values of implied bits in advance (before the multiplication operation) by examining the most significant bits of the mantissas. This preliminary determination allows the multiplication unit to proceed with the full multiplication using both explicit and implied bits simultaneously, eliminating the need for sequential processing and thereby improving processing speed without adding significant computational complexity.
2Productivity
If parallel processing of implied bits and multiplication is implemented, then processing speed improves, but hardware complexity increases
Solution Approach 1:
The patent merges the determination of implied bit values with the multiplication operation by having the multiplication unit perform both tasks in parallel. The multiplication unit simultaneously computes the product of explicit mantissa bits while another component determines implied bit values based on the most significant bits. This merging of functions into a single unified operation achieves parallel processing without proportionally increasing hardware complexity, as the same multiplication unit handles both tasks.
Solution Approach 2:
The multiplication unit determines its own implied bit values autonomously by examining its input operands (the most significant bits of the mantissas). This self-service capability eliminates the need for separate control logic or additional processing stages to determine implied bits, allowing parallel processing to proceed without proportionally increasing hardware complexity.
3Measurement precision
If more processing cycles are allocated for accurate floating-point multiplication, then calculation accuracy is improved, but memory bandwidth utilization decreases
Solution Approach 1:
By determining implied bit values in advance through preliminary examination of the most significant bits, the patent reduces the number of processing cycles required for the actual multiplication operation. This time optimization allows the system to complete floating-point multiplication faster, thereby improving memory bandwidth utilization without sacrificing calculation accuracy, as the preliminary bit determination ensures all necessary information is available for an accurate result.
Data Source
AI summary
A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.