Floating-Point Multiplier Parallel Implied-Bit Handling
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Solution Overview
Problem
Digital signal processors face challenges in efficiently handling real-time data processing due to limitations in memory access and scheduling, particularly in predictable but non-sequential input data patterns, which affect their performance in applications like video encoding.
Innovation Solution
The implementation of a streaming engine within the DSP core that manages data streams by generating addresses, performing data formatting, and optimizing memory access, allowing for parallel processing of implied bits during floating-point multiplication operations, thereby improving memory bandwidth and reducing cache miss stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sequential processing of floating-point multiplication is used, then processing accuracy is maintained, but processing speed decreases due to serial execution of implied bit determination and multiplication operations
Solution Approach 1:
The patent determines the values of implied bits of leading bit encoded mantissas in advance, before the actual multiplication operation begins. This preliminary determination allows the multiplication unit to proceed with the full multiplication including implied bits without waiting for sequential computation, thereby improving processing speed while maintaining accuracy
Solution Approach 2:
The patent transitions from sequential single-dimensional processing to parallel multi-dimensional processing by simultaneously determining implied bit values and performing multiplication operations. This dimensional change in processing architecture enables both operations to occur in parallel, resolving the speed-complexity contradiction
2Productivity
If parallel processing of implied bits and multiplication is implemented, then processing efficiency improves, but hardware resource requirements increase
Solution Approach 1:
The multiplication unit is designed to perform multiple functions: it can determine implied bit values and perform multiplication operations within the same hardware structure. This multi-functionality allows parallel processing to be achieved without proportionally increasing hardware resources, as the same unit handles both tasks concurrently
Solution Approach 2:
The patent merges the implied bit determination logic with the multiplication unit, combining what would traditionally be separate sequential operations into a single integrated parallel processing unit. This merging reduces overall hardware complexity compared to implementing completely separate parallel processing units
3Loss of time
If floating-point multiplication with implied bits is performed sequentially, then hardware complexity is minimized, but processing time increases affecting real-time performance
Solution Approach 1:
By determining implied bit values in advance before multiplication begins, the system eliminates the time penalty that would otherwise be incurred by sequential processing. This preliminary action ensures that all necessary information is ready for immediate parallel processing, reducing total processing time for real-time applications
Solution Approach 2:
The patent ensures continuous useful action by eliminating idle time between operations. While implied bits are being determined, other parts of the system can prepare for multiplication, and once implied bits are ready, multiplication begins immediately without interruption. This continuous processing minimizes processing time while managing architecture complexity
Data Source
AI summary
A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.