Floating-Point Multiply Circuit With Parallel Implied Bit Handling
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Solution Overview
Problem
Digital signal processors face challenges in efficiently handling real-time data processing due to memory bandwidth and scheduling constraints, particularly in applications involving predictable but non-sequential input data patterns, which can lead to delays in outputting transformed data streams.
Innovation Solution
A DSP processing core with an autonomous streaming engine that manages multiple data streams, supports vector-based operations, and includes a multiply circuit configured to perform implied bit handling in floating point multiplication, allowing parallel determination and multiplication of mantissa values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If floating point multiplication is performed using traditional sequential methods, then the multiplication operation can be completed with simpler circuit design, but the processing speed and productivity are reduced
Solution Approach 1:
The mantissa multiplication is segmented into multiple partial product groups, where each group is processed by separate second circuits in parallel. The mantissa is divided into segments that can be multiplied simultaneously, with each segment producing partial products that are later combined to form the final result.
Solution Approach 2:
The implied bits of the mantissas are determined in advance before the multiplication operation begins. This preliminary determination allows the multiply circuit to utilize all significant bits including implied ones, enabling more accurate and faster computation without requiring additional processing time during the multiplication itself.
2Measurement precision
If all bits including implied bits are used in mantissa multiplication, then the precision and accuracy of the result are improved, but the amount of computation and processing time increases
Solution Approach 1:
The values of implied bits are determined in advance during the operand preparation phase, before the actual multiplication occurs. This allows the full precision computation to be performed using all significant bits including implied ones, while the time-consuming bit determination is completed beforehand and does not add to the critical multiplication path delay.
Solution Approach 2:
The computation is segmented into parallel partial product calculations, where multiple second circuits simultaneously compute different segments of the multiplication using all significant bits. This parallel processing maintains high precision while reducing the overall computation time compared to sequential processing of all bits.
3Productivity
If parallel processing is implemented for determining implied bits and multiplying mantissas, then the processing speed is improved, but the circuit complexity and resource requirements increase
Solution Approach 1:
The parallel processing architecture is segmented into specialized functional units: third circuits for determining implied bits, second circuits for parallel partial product computation, and a fifth circuit for combining results. This segmentation allows each unit to be optimized for its specific function while working together in parallel to achieve high processing speed.
Solution Approach 2:
The multiply circuit is designed as a multi-functional unit that can perform both implied bit determination and mantissa multiplication operations within the same hardware structure. The circuit handles different aspects of floating point multiplication (exponent addition, mantissa multiplication with implied bits) in an integrated manner, reducing the need for separate dedicated circuits for each function.
Data Source
AI summary
Devices and methods are provided for performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers. In an example, a device includes a processor that includes a multiply circuit. The multiply circuit is configured to multiply floating point numbers in response to a floating point multiply instruction, and is further configured to determine values of implied bits of mantissas of the floating point numbers, and multiply the mantissas in parallel with the determining operation.