Floating-Point Multiplier Implied-Bit Handling With Parallel Paths
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Solution Overview
Problem
Digital signal processors face challenges in efficiently handling real-time data processing due to memory bandwidth and scheduling constraints, particularly in applications requiring predictable but non-sequential input data patterns, such as video encoding, where memory access and data processing are critical.
Innovation Solution
A processor architecture with dual scalar/vector data paths and an autonomous streaming engine that manages multiple data streams, including an address generation stage and data formatting, to improve memory bandwidth and data scheduling, supporting operations like vector-based finite impulse filtering, floating-point multiplication, and matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor handles memory access and data processing sequentially, then the processing logic is simple, but the processing speed and real-time performance deteriorate
Solution Approach 1:
The processor is divided into distinct functional components: an autonomous streaming engine for memory access operations and a processor core for data processing. This segmentation allows simultaneous execution of memory fetch tasks and processing operations, improving speed while maintaining manageable complexity through clear functional separation.
Solution Approach 2:
An autonomous streaming engine acts as an intermediary between memory and the processor core. It handles address generation, data formatting, and memory access tasks, freeing the processor core to focus on computation. This mediator enables parallel operation and improves overall system throughput.
2Productivity
If the processor performs all data processing functions, then processing completeness is ensured, but memory bandwidth utilization deteriorates
Solution Approach 1:
Memory access functions (address generation, data formatting, streaming control) are extracted from the processor core and implemented as an autonomous streaming engine. This extraction improves memory bandwidth utilization by dedicating specialized hardware to memory operations while reducing the processor core's functional complexity.
Solution Approach 2:
The streaming engine provides multi-functional support for various data formats and processing modes (scalar/vector, different precision formats) through a unified architecture. This universal design improves memory bandwidth utilization across diverse workloads without proportionally increasing complexity.
3Measurement precision
If floating point multiplication uses traditional bit handling, then implementation is straightforward, but processing precision and accuracy deteriorate
Solution Approach 1:
The floating point multiplication is divided into separate computational paths: one for determining implied bits and generating partial product terms, another for multiplying mantissa remainders. This segmentation improves precision by systematically handling each bit contribution while keeping individual path complexities manageable.
Solution Approach 2:
The patent introduces a fourth computational path for flush-to-zero mode calculation, adding a dimensional aspect to handle edge cases. This multi-dimensional approach ensures comprehensive precision coverage for all floating point scenarios without overwhelming complexity in any single path.
Data Source
AI summary
Devices and methods are provided for performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers. An example processor includes first, second, third, and fourth computational paths. In operation, the first determines values of implied bits of mantissas of floating point numbers and generates first partial product terms, the second multiplies remainders of the mantissas to generate second partial product terms, the third detects a number of leading zeros in the mantissas and determines a shift amount for each of the mantissas, and the fourth calculates exponents for a flush-to-zero mode.