Floating-Point Addition Conversion for Lower-Power AI MAC Units
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Solution Overview
Problem
Floating-point (FP) operations in AI applications are power-intensive and time-consuming, necessitating a reduction in power and area consumption for GPU, CPU, and hardware accelerators.
Innovation Solution
Transforming floating-point addition into integer addition by left-shifting the product and reducing the number of flip-flops in the MAC unit architecture, utilizing caching and left-shifting the mantissa product to optimize FP operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point operations are used in AI applications, then computation accuracy is maintained, but power consumption and area usage increase significantly
Solution Approach 1:
The patent transforms floating-point addition operations into integer addition operations by changing the numerical representation parameter. This is achieved by left-shifting the product and using integer arithmetic instead of floating-point arithmetic, thereby reducing power consumption while maintaining computational accuracy through careful management of the transformation process
Solution Approach 2:
The patent substitutes the floating-point computational mechanism with an integer-based mechanism. By replacing floating-point adders with integer adders and using left-shift operations instead of floating-point exponentiation, the system achieves lower power consumption and reduced area usage while preserving the essential computational functionality
2Measurement precision
If floating-point operations are used in AI applications, then computation accuracy is maintained, but processing time increases
Solution Approach 1:
The patent changes the operational parameter from floating-point arithmetic to integer arithmetic. By transforming the addition operation into an integer-based operation with left-shift, the processing time is reduced because integer operations are generally faster and simpler to execute than floating-point operations, while accuracy is maintained through the mathematical equivalence of the transformation
3Productivity
If floating-point dot product engine is implemented, then AI application performance is achieved, but area consumption increases
Solution Approach 1:
The patent changes the architectural parameter from floating-point processing units to integer processing units. By implementing the dot product engine using integer addition and left-shift operations instead of floating-point units, the area consumption is significantly reduced while maintaining AI application performance through the mathematical equivalence of the integer-based computation
4Measurement precision
If floating-point MAC unit architecture is used, then computational precision is maintained, but device complexity increases
Solution Approach 1:
The patent simplifies the device complexity by changing the operational parameter from floating-point to integer arithmetic. The MAC unit architecture is transformed to use integer addition and left-shift operations, which require simpler circuitry and fewer resources compared to floating-point MAC units, thereby reducing device complexity while maintaining computational precision through the transformation methodology
Data Source
AI summary
One embodiment provides a graphics processor comprising a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets include a matrix accelerator having circuitry to perform a floating-point operation including a plurality of floating-point multiplications. The circuitry includes input circuitry to store floating-point input values, a first adder to generate an intermediate exponent sum, a multiplier to generate an intermediate mantissa product, and an intermediate accumulator configured to accumulate a plurality of intermediate mantissa products as integer values within a plurality of rows of bitwise storage, the plurality of rows respectively associated with different exponent sums.