Floating Point MAC Precision Adjustment for Power Savings
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Solution Overview
Problem
Existing integer architectures for machine learning applications face scalability issues in performing dot product computations between large floating-point multiplicands, leading to increased complexity and power consumption, especially when full precision is required for intermediate results.
Innovation Solution
A pipelined floating-point multiplier-accumulator architecture with sign, exponent, and mantissa processors that dynamically adjust precision based on exponent differences, incorporating a maximum exponent finder and Pad, Complement, and Shift (PCS) stages to optimize multiplication and accumulation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full precision is used for intermediate results in floating point multiplication, then accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by making the precision of intermediate results variable rather than uniform. The precision is locally adapted to each multiplication operation based on the exponent difference between operands. When exponent difference is large, lower precision is used; when exponent difference is small, full precision is maintained. This resolves the contradiction by applying precision only where necessary.
Solution Approach 2:
The patent changes the precision parameter dynamically based on the exponent difference between input floating point numbers. The system calculates the exponent difference and uses it to determine the number of bits to retain in intermediate results. This parameter change allows the system to reduce precision (and power consumption) when full precision is not needed, while maintaining full precision when accuracy is critical.
2Measurement precision
If high precision intermediate results are maintained, then final result accuracy is improved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by applying different processing paths based on local conditions (exponent difference). The architecture includes control logic that determines precision requirements and configures the computation pipeline accordingly. This avoids the need for a single complex high-precision path for all operations.
Solution Approach 2:
The patent introduces dynamic precision adjustment mechanisms that adapt the computational architecture to the specific requirements of each operation. The system dynamically selects between different precision levels and corresponding computational paths, making the architecture flexible rather than statically complex.
3Use of energy by moving object
If precision is reduced for power savings, then power consumption decreases, but accuracy of the final result may deteriorate
Solution Approach 1:
The patent uses parameter changes (exponent difference) as the basis for determining precision reduction. By analyzing the exponent difference between inputs, the system predicts when precision reduction will not affect final accuracy. This ensures power savings are achieved only when mathematically safe to do so.
Solution Approach 2:
The patent incorporates feedback mechanisms where the exponent difference calculation informs the precision selection, and the system monitors whether precision reduction maintains sufficient accuracy. This feedback loop ensures that accuracy requirements are met while maximizing power savings.
4Productivity
If scalable architecture is implemented for large N operations, then productivity increases, but device complexity increases
Solution Approach 1:
The patent segments the computational task into N parallel processing elements, each handling one multiplication-accumulation operation. This segmentation enables scalable processing of large dot products while maintaining manageable complexity at each segment. The parallel structure improves productivity without requiring a monolithic complex design.
Solution Approach 2:
The patent creates universal processing elements that can handle different precision requirements through configuration rather than requiring separate hardware for each precision level. This multi-functionality allows the same segmented architecture to adapt to varying computational needs, improving productivity without proportionally increasing complexity.
Data Source
AI summary
A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates an integer form fraction accompanied by a sign bit and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. A range estimating process determines a possible range of values from the exponent differences and determines an adder precision. A summing process adds all of the integer form fractions using the determined adder precision, and converts the sum to a floating point value using the maximum exponent sum, sign bit of the summed integer form fractions, and optionally performs a 2's complement of the summed integer form fraction if the sign bit is negative.