Floating-Point Multiply-Accumulate Unit for AI Processors
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Solution Overview
Problem
Current artificial intelligence processors using nonvolatile memory-based Processing-In-Memory (PIM) architecture face challenges with high power consumption and complexity in performing floating-point operations, which are essential for efficient artificial neural network computations.
Innovation Solution
A floating-point multiply-accumulate operation method and apparatus that utilize a Magnetoresistive Random Access Memory Computing-In-Memory (MRAM-CIM) core and high precision neural core to perform exponent and mantissa operations, shifting, accumulation, overflow handling, normalization, and rounding, optimizing power efficiency and computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point operations are implemented in conventional AI processors, then computational precision is improved, but power consumption increases significantly
Solution Approach 1:
The floating-point operation is segmented into separate exponent and mantissa processing stages. The exponent adder handles exponent operations while the mantissa multiplier handles significand operations independently, allowing parallel processing and reducing overall power consumption while maintaining precision.
Solution Approach 2:
An accumulation register is introduced as an intermediary component to store intermediate results of mantissa additions. This allows the system to accumulate precision across multiple operations without immediately writing back to memory, reducing power consumption from memory access operations while maintaining computational accuracy.
2Measurement precision
If floating-point operations are implemented in AI processors, then computational accuracy is improved, but device complexity increases
Solution Approach 1:
The floating-point unit is segmented into distinct functional blocks: exponent adder, mantissa multiplier, mantissa adder, and accumulation register. Each block performs a specific function with simple logic, avoiding the need for a complex general-purpose floating-point unit while achieving the same computational accuracy.
Solution Approach 2:
The system performs partial floating-point operations by maintaining separate exponent and mantissa processing paths rather than implementing a complete IEEE 754 compliant FPU. This partial implementation achieves sufficient accuracy for AI workloads while dramatically reducing device complexity.
3Use of energy by moving object
If nonvolatile memory-based PIM architecture is used, then power efficiency is improved for fixed-point operations, but adaptability to floating-point operations deteriorates
Solution Approach 1:
The PIM architecture is enhanced with a hybrid computational unit that can handle both fixed-point and floating-point operations. The exponent adder, mantissa multiplier, and accumulation register work together to provide universal floating-point capability while maintaining the power-efficient characteristics of the underlying nonvolatile memory PIM architecture.
Solution Approach 2:
The system changes operational parameters dynamically by switching between fixed-point and floating-point modes. When floating-point operations are required, the exponent and mantissa processing paths are activated, while the core PIM architecture remains unchanged, preserving power efficiency while gaining floating-point adaptability.
Data Source
AI summary
An embodiment of the present disclosure may provide a multiply-accumulate operation method performed by a multiply-accumulate operation apparatus, the multiply-accumulate operation method including accumulating, by an accumulation register, a value within a preset bit value of a mantissa bitwidth in a result of an addition operation of a shifted first mantissa value and a shifted second mantissa value, determining, by an overflow counter, an overflow count based on an overflow value by which the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bitwidth, performing normalization and rounding based on the value accumulated in the accumulation register and the overflow count, and updating, by an exponent updater, the exponent using a normalized and rounded value.