Floating Point Conversion Using a Magic Addend for Correct Rounding
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Solution Overview
Problem
Converting floating point representations between different precisions, such as from single precision to half precision, is challenging due to the lack of hardware support in desktop CPUs, leading to slow, inexact, or erroneous results, especially when handling subnormal values and requiring correct rounding modes, which can cause data drift and performance bottlenecks.
Innovation Solution
A method using a floating point adder to convert single precision to half precision through a single add operation with a 'magic value' determined from the input value's sign and exponent fields, allowing correct rounding and handling of subnormal values without stalls, using either real-time calculation or a lookup table, and supporting IEEE-754 rounding modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional software conversion methods are used to convert single precision to half precision floating point format, then conversion accuracy can be maintained with correct rounding modes, but conversion speed becomes very slow due to requiring a large number of instructions
Solution Approach 1:
The patent changes the fundamental parameter of the conversion approach from sequential software instructions to a single hardware floating point add operation. By reformulating the conversion problem as an addition operation with a carefully chosen magic value, the patent achieves both high speed (single operation) and high accuracy (correct rounding through IEEE-754 compliant adder), resolving the contradiction between speed and accuracy
Solution Approach 2:
The patent introduces a magic value as an intermediary element that enables the conversion. This magic value, when added to the single precision input, produces a result where the lower 16 bits contain the correctly rounded half precision output. The magic value acts as a mediator that transforms the conversion problem into a simple addition operation while preserving accuracy
2Productivity
If hardware conversion support is provided (as in GPUs and mobile phones), then conversion speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent makes the existing floating point adder unit universal by enabling it to perform both its original addition function and the new conversion function. The same hardware circuit can convert single precision to half precision by simply changing the input operands (adding a magic value), eliminating the need for dedicated conversion hardware and reducing device complexity while maintaining high speed conversion
3Measurement precision
If correct IEEE-754 rounding mode is enforced during conversion, then conversion accuracy is maintained, but handling of subnormal values creates performance bottlenecks due to stalls
Solution Approach 1:
The patent converts the potential harm of subnormal values (which typically cause stalls and performance degradation) into a benefit. By using the magic value addition approach, subnormal inputs are naturally handled correctly through the same single add operation that processes normal values. The IEEE-754 compliant adder automatically produces correctly rounded results including for subnormal cases, eliminating stalls while maintaining accuracy
Data Source
AI summary
A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number.