Floating-Point Max Min Circuit Encoding Status Bits
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Solution Overview
Problem
Existing floating-point units face issues with implicit serialization and difficulty in optimizing floating-point operations due to global flags and traps, particularly when performing maximum or minimum operations, which can lead to incorrect results and serialization problems in parallel processing architectures.
Innovation Solution
A floating-point max/min circuit that encodes floating-point status information within the result, allowing for simultaneous execution of instructions without overwriting status information, and correctly handles NaN, infinity, and zero cases while maintaining mathematical identities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global flags and traps are used to track floating-point status information, then floating-point operations can be monitored and controlled, but implicit serialization occurs and parallel processing efficiency is reduced
Solution Approach 1:
The patent divides the floating-point status information into separate per-operand fields within the result itself, rather than using shared global flags. Each floating-point operand contains its own status bits (such as NaN, infinity, zero indicators) that can be independently processed, eliminating the serialization caused by global state and enabling parallel processing of multiple operations.
Solution Approach 2:
The patent extracts status information from global flags and embeds it directly into the floating-point result operands. By moving the status bits from a shared global location into the individual result structures, the system eliminates the bottleneck of global state access and allows simultaneous execution of multiple floating-point instructions.
2Productivity
If maximum or minimum operations are performed using conventional floating-point units, then arithmetic results are produced, but incorrect results occur for special cases like NaN and infinity
Solution Approach 1:
The patent performs preliminary classification of floating-point operands by examining their status bits (NaN, infinity, zero indicators) before executing maximum or minimum operations. This preliminary action allows the system to route special cases through appropriate handling logic, ensuring correct results for NaN comparisons, infinity operations, and zero cases while maintaining efficient processing for normal numbers.
Solution Approach 2:
The patent applies different processing rules to different types of floating-point operands based on their local characteristics. Normal numbers follow standard comparison rules, while NaN values are handled according to IEEE 754 specifications (typically propagating NaN), infinity values are compared by magnitude and sign, and zero cases (including signed zero) are treated with special attention to maintain mathematical identities.
3Loss of information
If status information is stored separately from floating-point results, then status tracking is possible, but optimization of floating-point code becomes difficult
Solution Approach 1:
The patent merges status information directly into the floating-point result operands by embedding status bits within the result structure itself. This combination eliminates the need for separate status registers and flag management, allowing compilers and optimizers to treat status information as intrinsic part of the data, thereby simplifying code generation and optimization while preserving all necessary status information.
Data Source
AI summary
A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.