Floating-Point Multiplication Circuitry for Mixed-Precision Throughput
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Solution Overview
Problem
Specialized processing blocks in integrated circuits often lack efficient support for both single-precision and half-precision floating-point arithmetic operations, leading to inefficiencies in power consumption and functional density, particularly in applications like convolutional neural networks.
Innovation Solution
Implementing a specialized processing block with single-precision floating-point multiplication circuitry that includes first, second, and third arithmetic operator circuits, a compressor circuit, and combinational logic to generate partial products and anticipate rounding and normalization operations, allowing simultaneous generation of sum-plus-zero, sum-plus-one, and sum-plus-two signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If specialized processing blocks use fixed-point operators for arithmetic operations, then device complexity is reduced and power consumption decreases, but adaptability for floating-point operations is lost
Solution Approach 1:
The specialized processing block implements dynamic configuration of arithmetic operators that can switch between fixed-point and floating-point modes. The arithmetic operators are designed to be reconfigurable, allowing the same hardware structure to adapt its behavior based on the input data type, thereby providing floating-point support without permanently increasing device complexity.
Solution Approach 2:
The arithmetic operator circuits are designed as universal structures capable of performing both fixed-point and floating-point operations. By making the operators multi-functional, the patent eliminates the need for separate dedicated circuits for each operation type, thus improving adaptability while controlling device complexity through resource sharing.
2Adaptability or versatility
If floating-point operators are constructed outside specialized processing blocks using general-purpose programmable logic, then floating-point operation capability is achieved, but productivity and power efficiency deteriorate
Solution Approach 1:
The floating-point arithmetic capability is segmented and integrated directly into the specialized processing block's arithmetic operators rather than being implemented as a separate external unit. This segmentation allows the floating-point operations to be performed in parallel with other specialized block operations, improving overall productivity and throughput.
Solution Approach 2:
The patent merges the floating-point operator functionality with the existing specialized processing block architecture. By combining these functions into a unified structure, the patent enables simultaneous execution of specialized operations and floating-point operations, thereby improving productivity compared to sequential processing in separate units.
3Adaptability or versatility
If specialized processing blocks support both single-precision and half-precision floating-point operations, then adaptability improves, but device complexity and power consumption increase
Solution Approach 1:
The arithmetic operators are designed with dynamic precision selection capability, allowing them to switch between single-precision and half-precision modes based on input data. This dynamic adaptation enables multi-precision support without requiring permanently configured circuits for each precision level, thereby controlling device complexity.
Solution Approach 2:
The patent implements parameter-based configuration of arithmetic operators where precision mode (single or half) is controlled by configurable parameters. By changing operational parameters rather than hardware structure, the system achieves multi-precision adaptability while minimizing increases in device complexity.
4Productivity
If rounding and normalization operations are performed sequentially after multiplication, then manufacturing precision is maintained, but productivity decreases due to sequential processing
Solution Approach 1:
The patent performs preliminary preparation of data for rounding and normalization operations during the multiplication process itself. By anticipating and pre-processing certain aspects of the final result generation, the system enables parallel execution of multiplication and preliminary rounding/normalization steps, improving productivity while maintaining precision through controlled approximation.
Solution Approach 2:
The arithmetic operators maintain continuous operation by overlapping multiplication with preliminary rounding and normalization preparation. This continuous useful action eliminates idle time between operations and maintains precision by ensuring that approximation steps are systematically integrated rather than interrupting the computational flow.
Data Source
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AI summary
The present embodiments relate to performing reduced- precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial product of first and second input signals, while a second partial product generator may generate a second partial product of third and fourth input signals. A compressor circuit may generate carry and sum vector signals based on the first and second partial products; and circuitry may anticipate rounding and normalization operations by generating in parallel based on the carry and sum vector signals at least two results when performing the single-precision floating-point operation and at least four results when performing the two half-precision floating-point operations.