Floating Point Multiplication with Extension Bit for Neural Networks
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Solution Overview
Problem
Neural network devices face high energy consumption due to frequent memory access for processing large amounts of complex data, which is particularly challenging for low-power devices like mobile and IoT systems.
Innovation Solution
A processor-implemented method for floating point multiplication that normalizes binary values, determines if they are representable in a given format, and encodes them using an extended bit format to extend the dynamic range, allowing for efficient processing and reduced energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If floating point multiplication is performed using standard n-bit format, then computation speed is improved, but accuracy is lost for extended normal numbers
Solution Approach 1:
The patent extends the dynamic range by adding an extension bit to the floating point format, transitioning from n-bit to (n+1)-bit representation. This dimensional change allows extended normal numbers to be represented without sacrificing computation speed, as the extended format is seamlessly integrated into the multiplication pipeline.
Solution Approach 2:
The patent modifies the floating point format parameters by introducing an extension bit that indicates whether a number is an extended normal number. This parameter change enables the system to represent a broader range of values while maintaining the same computation speed characteristics as the original n-bit format.
2Measurement precision
If extended bit format is used to represent extended normal numbers, then accuracy is improved, but circuit area increases
Solution Approach 1:
The patent segments the floating point representation into standard n-bit format and an additional extension bit. This segmentation allows the system to use the extended format only when necessary (for extended normal numbers), minimizing the average circuit area impact while maintaining accuracy for these special cases.
Solution Approach 2:
The extension bit acts as a lightweight, minimal-cost addition to the floating point format. Rather than redesigning the entire n-bit format, the patent uses a simple disposable extension element that provides accuracy enhancement only when needed, keeping the overall circuit area increase minimal.
3Measurement precision
If extended bit format is implemented, then floating point accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies partial extension by using the extended bit format only for extended normal numbers rather than all floating point operations. This selective approach reduces the average power consumption compared to always using an extended format, while still providing accuracy improvements where needed.
Solution Approach 2:
The extension bit automatically indicates when extended normal number handling is required, allowing the system to self-adjust its processing mode. This self-service mechanism minimizes additional power consumption by avoiding unnecessary extended format processing for standard numbers.
4Device complexity
If standard n-bit format is used, then device complexity is reduced, but dynamic range is limited
Solution Approach 1:
The patent nests the extension bit within the existing n-bit floating point format structure. The extended format contains the original n-bit format as a subset, allowing the system to maintain compatibility with standard formats while extending the dynamic range for special cases without significantly increasing overall complexity.
Solution Approach 2:
The extension bit serves multiple functions: it extends the dynamic range for extended normal numbers, maintains backward compatibility with standard n-bit formats, and provides a clear indication mechanism for different number types. This multi-functionality achieves enhanced adaptability without proportionally increasing device complexity.
Data Source
AI summary
A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.