Floating Point Multiplication Rounding and Underflow Detection
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Solution Overview
Problem
Existing floating-point multiplication methods require serial processing and are inefficient in performing rounding evaluation and increment without waiting for the final product, and struggle with detecting underflow conditions, especially near the subnormal/normal boundary, leading to increased costs and complexity.
Innovation Solution
A data processing apparatus using half adder logic to produce carry and sum bits from 2n-bit vectors, with first and second adder logic performing sum operations with rounding increments at specific positions to derive n-bit results, and selector logic to determine if the result is in the subnormal range or overflow condition, allowing for efficient rounding and underflow detection before the final product is produced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial processing is used for floating-point multiplication, then the processing steps are simple to implement, but the processing time is excessive and efficiency is low
Solution Approach 1:
The patent performs rounding evaluation and determines whether rounding increment is needed before the final product is fully produced. The exponent determination logic evaluates the product exponent early, and the selector logic determines the rounding mode in advance, allowing the rounding increment to be injected into the adder logic without waiting for the complete multiplication result. This preliminary action reduces the critical path delay and improves processing efficiency.
Solution Approach 2:
The patent divides the floating-point multiplication process into independent parallel segments: exponent addition, significand multiplication, rounding evaluation, and result selection. These segments can be executed simultaneously rather than sequentially. The rounding evaluation logic operates independently on the exponent information, while the significand multiplication produces the final product, and the selector logic chooses the appropriate rounding behavior based on pre-evaluated conditions.
2Measurement precision
If rounding evaluation is performed after the final product is produced, then the calculation is straightforward, but the processing time increases
Solution Approach 1:
The patent determines the rounding evaluation result and whether a rounding increment is needed before the final product is fully produced. The exponent determination logic evaluates the product exponent in advance, and the selector logic determines the appropriate rounding mode (round toward zero, away from zero, to nearest even, or to infinity) before the addition is complete. This allows the rounding increment to be injected into the adder logic during the addition process itself, rather than requiring a separate post-processing step.
3Reliability
If full adder logic is used for all bit positions, then the addition is complete and accurate, but the device complexity and cost increase
Solution Approach 1:
The patent uses different adder logic types for different bit positions based on local requirements. Full adder logic is used only at the rounding increment injection position where three inputs are needed (two operand bits and the rounding increment bit). For all other bit positions, half adder logic is sufficient since only two inputs are needed. This local differentiation reduces the overall device complexity and cost while maintaining addition accuracy, as the more complex full adder is used only where absolutely necessary.
4Measurement precision
If underflow detection is performed near the subnormal/normal boundary, then the detection is accurate, but the costs and complexity increase
Solution Approach 1:
The patent performs underflow detection by evaluating the product exponent in advance, before the final product is produced. The exponent determination logic calculates the product exponent from the input exponents and compares it against predefined thresholds that define the subnormal/normal boundary. This preliminary exponent evaluation provides accurate underflow detection without requiring complex circuitry to analyze the full significand product, as the exponent alone suffices to determine whether the result will be subnormal or normal.
Data Source
AI summary
The first and second n-bit significands are multiplied producing a pair of 2n-bit vectors, and half adder logic produces a corresponding plurality of carry and sum bits. A product exponent is checked for correspondence with a predetermined exponent value. A sum operation generates a first result equivalent to the addition of the pair of 2n-bit vectors. First adder logic uses corresponding m carry and sum bits, the least significant of them carry bits being replaced with the increment value prior to the first adder logic performing the first sum operation. Second adder logic performs a second sum operation and uses the corresponding m−1 carry and sum bits replacing the least significant m−1 carry bits with the rounding increment value prior to the second adder logic second sum operation. The n-bit result is derived from either the first rounded result, the second rounded result or a predetermined result value.